MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1410
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Multimaster operation 15-27
Multiphase motor commutation (COMM) D-17
Multiple end-of-queue 13-40
multiple input signature calculator (MISC) 20-8
Multiplexed
multiplexing
MUX 13-15
N
VFLSn and MPIO32B 23-30
Negative stress 13-76
New
New input capture/transistion counter (NITC) D-15
NEWQP 15-20
NF 15-50
NI bit 3-16
NITC D-15
Noise
Non-IEEE floating-point operation 3-16
nonoptional instructions, 3-40
Non-recoverable interrupt 3-25
NOT ACTIVE
Not ready (NOTRDY) 16-21
NOTRDY 16-18
NRI 3-25
O
OC D-42
OE bit 3-15
OP0 9-30
OP1 9-30
OP2 9-30
OP3 9-30
Open drain drivers 14-66
operand placement (effects), 3-43
operand representation (illustration), 9-30
Operating Environment Architecture (Book 3)
Index-10
analog inputs 13-7
signals 2-20
queue pointer value (NEWQP) 15-20
parameters D-15
error flag (NF) 15-50
errors 15-57
flag (NF) 15-57
receive message buffer code 16-5
branch processor, 3-44
exceptions, 3-45
fixed-point processor
fixed-point processor, 3-44
slave edge-aligned mode D-23
special purpose registers, 3-44
non-inverted center aligned mode D-48
,
15-57
,
15-25
,
16-21
,
,
14-6
14-74
,
14-41
MPC561/MPC563 Reference Manual, Rev. 1.2
Operating Environment Architecture (OEA) 3-44
optional instructions, 3-40
OR 15-50
OR registers 10-34
Ordered exceptions 3-35
OTR 24-8
Output compare (OC) D-42
OV (overflow) bit 3-18
Overload frames 16-17
OVERRUN
Overrun error (OR) 15-50
OX bit 3-14
P
P 13-30
parameter RAM 19-3
Parity
Pause (P) 13-30
PCBK 19-14
PCS 15-24
PCS0/SS 15-39
PCS3-PCS0/SS 15-42
PDMCR 2-22
PDMCR2 2-23
PE 15-47
performance
Period
Periodic interrupt
Periodic/interval timer 13-51
Peripheral
Peripheral Chip-Select 3-0/Slave Select
PF 15-50
PF1 13-22
PF2 13-23
optional facilities and instructions, 3-61
storage control instructions, 3-45
timer facilities, 3-61
receive message buffer code 16-5
(PF) flag 15-57
checking 15-53
enable (PE) 15-47
error (PF) bit 15-50
errors 15-57
type (PT) 15-47
type (PT) bit 15-53
to SCK delay (DSCK) 15-24
L-bus 11-10
/pulse-width accumulator (PPWA) D-38
timer 6-20
continuous-scan mode 13-47
chip-selects (PCS) 15-24
(PCS3-PCSO/SS) 15-42
,
14-31
,
15-57
,
,
14-23
14-24
,
13-38
,
19-23
,
14-31
,
15-37
,
,
14-50
14-39
,
14-48
Freescale Semiconductor
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