MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 299

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

7.5.2
Following is the hard reset configuration word that is sampled from the internal data bus,
data_sgpiod(0:31) on the negation of HRESET. If the external reset config word is selected (RSTCONF =
0), the internal data bus will reflect the state of external data bus. If the internal reset config word is selected
and neither of the Flash reset config words are enabled (UC3FCFIG[HC] = 1), the internal data bus is
internally driven with all zeros. The reset configuration word is not a register in the memory map. Most of
the bits in the configuration are located in registers in the SIU. Refer to
of each control bit.
Freescale Semiconductor
1
HRESET
HRESET
Available only on the MPC562/MPC564, software should write "0" to this bit for MPC561/MPC563.
Bits
Field EARB
Field PRPM
0
1
2
3
Hard Reset Configuration Word (RCW)
MSB
16
Name
EARB
BDRV
0
BDIS
IP
IP BDRV BDIS
17
1
SC
External Arbitration — Refer to
Bus arbitration. The default value is that internal arbitration hardware is used.
0 Internal arbitration is performed
1 External arbitration is assumed
Initial Interrupt Prefix — This bit defines the initial value of MSR[IP] immediately after reset.
MSR[IP] defines the Interrupt Table location. If IP is zero then the initial value of MSR[IP] is zero,
If the IP is one, then the initial value of MSR[IP] is one. Default value is zero. See
more information.
0 MSR[IP] = 0 after reset
1 MSR[IP] = 1 after reset
Bus Pins Drive Strength — This bit determines the bus pins (address, data and control) driving
capability to be either full or reduced drive. The bus default drive strength is full; Upon default, it
also effects the CLKOUT drive strength to be full. See
controls the default state of COM1 in the SIUMCR.
0 Full drive
1 Reduced drive
Boot Disable — If the BDIS bit is set, then memory controller is not activated after reset. If it is
cleared then the memory controller bank 0 is active immediately after reset such that it matches
any addresses. If a write to the OR0 register occurs after reset this bit definition is ignored. The
default value is that the memory controller is enabled to control the boot with the CS0 pin. See
Section 10.7, “Global (Boot) Chip-Select
0 Memory controller bank 0 is active and matches all addresses immediately after reset
1 Memory controller is not activated after reset.
18
2
ETRE FLEN
Figure 7-7. Reset Configuration Word (RCW)
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 7-5. RCW Bit Descriptions
20
4
BPS[0:1]
COMP
EN_
21
5
1
0000_0000_0000_0000
0000_0000_0000_0000
Section 9.5.7, “Arbitration
COMP
EXC_
22
6
1
—
Operation,” for more information.
Description
—
23
7
24
8
OERC
DBGC[0:1]
25
9
Table 6-7
Table 7-5
Phase,” for a detailed description of
10
26
—
for more information. BDRV
—
11
27
for a detailed description
ATWC EBDF[0:1]
12
28
ISB
13
29
Table 3-11
14
30
DME
for
LSB
—
15
31
Reset
7-11