MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 213
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
MPC561MZP56R2
Manufacturer:
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4.2.6
When the MPC561/MPC563 RCPU core is in debug mode, the BBC initiates non-burstable access to the
debug port and ICDU is bypassed (i.e., instructions transmitted to the debug port must be non-compressed
regardless of RCPU MSR[DCMPEN] bit state).
4.3
The BBC is able to relocate the exception addresses of the RCPU. The relocation feature always maps the
exception addresses into the internal memory space of the MPC561/MPC563. See
is important in multi-MPC561/MPC563 systems, where, although the memory map in some was shifted
to not be on the lower 4 Mbytes, their RCPU cores can still access their own exception handlers in their
internal Flash in spite of several RCPUs issuing the same exception addresses.
The relocation also saves wasted space between the exception table entries in the case where each
exception entry contained only a branch instruction to the exception routine, which is located elsewhere.
The exception vector table may be programmed to be located in four places in the MPC561/MPC563
internal memory space.
The exception table relocation is supported in both decompression on and decompression off operation
modes.
The RESET routine vector is relocated differently in decompression on and in decompression off modes.
This feature may be used by a software code compression tool to guarantee that a vocabulary table
initialization routine is always executed before application code is running.
Freescale Semiconductor
Exception Table Relocation (ETR)
Debug Operation Mode
Because HRESET resets the EN_COMP bit and the EXC_COMP bit but
SRESET does not, there may be different behavior between HRESET and
SRESET when both EN_COMP and EXC_COMP are set. Special care must
be taken to ensure operation in a known mode whenever reset occurs. The
reset states of these bits are determined by reset configuration words. The
location of the reset vector is dependent on the value of the MSR[IP] bit in
the RCPU. If MSR[IP] is set, the exception table relocation feature can be
used. See
Section 4.3.1, “ETR
MPC561/MPC563 Reference Manual, Rev. 1.2
Operation.”
NOTE
Burst Buffer Controller 2 Module
Figure
4-2. This feature
4-7
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