MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 342

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

External Bus Interface
then controls the length of the cycle with the signal(s) used to terminate the cycle. A strobe signal for the
address lines indicates the validity of the address.
The MPC561/MPC563 bus is synchronous with a synchronous support. The bus and control input signals
must be timed to setup and hold times relative to the rising edge of the clock. Bus cycles can be completed
in two clock cycles.
For all inputs, the MPC561/MPC563 latches the level of the input during a sample window around the
rising edge of the clock signal. This window is illustrated in
Figure
9-1, where t
and t
are the input
su
ho
setup and hold times, respectively. To ensure that an input signal is recognized on a specific rising edge of
the clock, that input must be stable during the sample window. If an input makes a transition during the
window time period, the level recognized by the MPC561/MPC563 is not predictable; however, the
MPC561/MPC563 always resolves the latched level to either a logic high or low before using it. In
addition to meeting input setup and hold times for deterministic operation, all input signals must obey the
protocols described in this section.
t
ho
t
su
Clock
Signal
Sample
Window
Figure 9-1. Input Sample Window
9.3
Bus Control Signals
The MPC561/MPC563 initiates a bus cycle by driving the address, size, address type, cycle type, and
read/write outputs. At the beginning of a bus cycle, TSIZ[0:1] are driven with the address type signals.
TSIZ0 and TSIZ1 indicate the number of bytes remaining to be transferred during an operand cycle
(consisting of one or more bus cycles). These signals are valid at the rising edge of the clock in which the
transfer start (TS) signal is asserted.
The read/write (RD/WR) signal determines the direction of the transfer during a bus cycle. Driven at the
beginning of a bus cycle, RD/WR is valid at the rising edge of the clock in which TS is asserted. The logic
level of RD/WR only changes when a write cycle is preceded by a read cycle or vice versa. The signal may
remain low for consecutive write cycles.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-2
Freescale Semiconductor