MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1409
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
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Manufacturer:
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message
messaging
MI_GRA 4-23
MI_RA [0:3] 4-22
MI_RBA[0:3] 4-21
MIOS14
MIOS14ER0 17-66
MIOS14ER1 17-68
MIOS14LVL0 17-69
MIOS14LVL1 17-70
MIOS14MCR 17-15
MIOS14RPR0 17-67
MIOS14RPR1 17-68
MIOS14SR0 17-66
MIOS14SR1 17-67
MIOS14TPCR 17-14
MIOS14VECT 17-14
MIOS14VNR 17-14
MISC 20-8
MISCNT 20-6
MISO 15-34
MISRH 20-5
MISRL 20-5
MMCSM 17-19
MMCSMCNT 17-23
MMCSMML 17-24
MMCSMSCR 17-24
MMCSMSCRD 17-24
Mode
Mode Fault Flag (MODF) 15-42
Modes
modes
Freescale Semiconductor
format error (FORMERR) 16-34
CAN bus transmission 16-13
READI 24-4
16-bit parallel port I/O submodule (MPIOSM) 17-60
bus interface submodule (MBISM) 17-13
counter prescaler submodule (MCPSM) 17-16
double action submodule (MDASM) 17-26
interrupt request submodule (MIRSM) 17-64
interrupts 17-63
modulus counter submodule (MMCSM) 17-19
pulse width modulation submodule (MPWMSM) 17-46
fault flag (MODF) 15-22
select (M) 15-47
stop 14-8
BBC operation 4-4
CALRAM operation 22-4
censorship modes of UC3F 21-31
clock frequency for each 8-17
code decompression A-14
debug
,
15-39
,
24-22
,
15-27
MPC561/MPC563 Reference Manual, Rev. 1.2
,
17-70
MODF 15-22
module configuration register (QADC64E) 13-8
module configuration register (QADCMCR) 14-8
Modulus
MOSI 15-34
Most significant bit (MSB) 13-36
MPC561/MPC563
VFLSn and MPIO32B 23-30
MPIOSM 17-60
MPIOSMDDR 17-63
MPIOSMDR 17-62
MPWMCNTR 17-58
MPWMPERR 17-57
MPWMPULR 17-58
MPWMSCR 17-58
MQ1 13-16
MQ2 13-18
MSB 13-36
MSR 3-20
MSTAT registers 10-32
MSTR 15-18
Multichannel pulse-width modulation (MCPWM) D-22
DECRAM
disabled 13-41
DPTRAM operation 20-6
external master 6-4
freeze 13-9
interrupt controller enhanced operation 6-11
interrupt controller regular operation 6-10
JTAG 25-3
L2U operation 11-3
limp support 8-14
low power 8-16
low-power 6-23
MIOS14 MDASM operation 17-3
MPC561/563 development support signals 2-29
READI 24-3
reserved 13-41
scan. See Scan modes
stop 13-9
TOUCAN 16-17
counter 15-52
block diagram 1-2
differences from MPC555 1-9
memory map 1-11
optional features 1-9
parameters
operation of BBC 4-7
standby operation 4-14
3-56
D-30
slave channel A
,
3-57
,
3-46
,
,
,
,
14-17
14-19
14-38
,
15-39
,
15-27
3-59
,
,
,
3-48
14-42
14-42
,
,
3-60
15-42
,
3-49
,
3-50
,
,
3-52
14-38
,
17-29
,
3-53
,
3-54
,
Index-9
3-55
,
,
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