MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 867

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

21.2
The UC3F EEPROM module consists of a control register block, an addressable shadow row implemented
in Flash, and an addressable main Flash memory array. The control registers are used to configure,
program, erase and exercise the UC3F shadow row and Flash array.
21.2.1
These supervisor-level control registers are used to control UC3F EEPROM module operation. On reset,
the registers are loaded with default reset information. Several bits of the UC3F control registers are
special Flash NVM registers which retain their state when power is removed from the UC3F EEPROM.
These special NVM registers are identified in the individual register field and control bit descriptions.
21.2.1.1
The UC3F module control registers, shown in
generated from the BIU. As such, each Flash module that is designed using the UC3F EEPROM module
may uniquely define the addressing of the control register block.
21.2.1.2
The UC3F module configuration register is used to configure the operation and access restrictions of the
UC3F array and shadow row.
Freescale Semiconductor
HRESET
HRESET
Field STOP LOCK
Field
Addr
Programming Model
UC3F EEPROM Control Registers
1
Register Addressing
UC3F EEPROM Configuration Register (UC3FMCR)
MSB
Reset state determined by NVM registers. These bits will be set to 01 by the factory.
16
0
0
0
17
Figure 21-2. UC3F EEPROM Configuration Register (UC3FMCR)
1
0
1
0x2F C80C
0x2F C800
0x2F C804
0x2F C808
Address
—
18
0
0
2
Table 21-2. UC3F Register Programming Model
MPC561/MPC563 Reference Manual, Rev. 1.2
FIC
19
0
0
3
DATA
SIE
20
0
0
4
ACCESS CENSOR
Table
21
0
0
5
Module Configuration (UC3FMCR)
Extended Module Configuration (UC3FMCRE)
High Voltage Control (UC3FCTL)
Reserved
0x2F C800
21-2, are selected with individual register selects
1
22
0
6
1
1
23
0
7
1
24
1
1
8
25
1
1
9
Register
10
26
1
1
PROTECT
11
27
1
1
SUPV
CDR3 Flash (UC3F) EEPROM
12
28
1
1
13
29
1
1
14
30
1
1
LSB
15
31
1
1
21-5