MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1036

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

READI Module
the RWA register, and transmits the SC, RWAD, RW fields only is sufficient. This message will contain
41 bits instead of the 94 bits for writing the full contents of the RWA register. See
Section 24.6.4, “Partial Register
24.10.10 Throughput and Latency
Throughput analysis has been performed for various read/write access cases such as single write, block
write, single byte read, single word read, block byte read, block word read accesses to memory-mapped
locations. Data is presented for the two cases when the RWA register is written partially and completely.
24.10.10.1 Assumptions for Throughput Analysis
24-68
•
•
•
•
•
•
•
•
Single Write Access to memory-mapped
location – Word and Byte access
(In Million Messages Per Second)
Single Read Access to memory-mapped
location – Word access
(In Million Messages Per Second)
Single Read Access to memory-mapped
location – Byte access
(In Million Messages Per Second)
Block Write Access to memory-mapped
locations – 64-Kbyte block (Word and Byte) write
access
(In 64-Kbyte Block Writes Per Second)
All accesses are single read accesses only.
MCKI running at 28 MHz.
MCKO running at 56 MHz.
56-MHz internal operation.
Five clock internal L-bus access (read)
Output signals always free (not in middle of transmission) when requested.
One idle clock between read messages.
No delay from tool in responding — tool keeps up with READI port.
Table 24-31. Throughput Comparison for FPM and RPM MDO/MDI Configurations
The last data bit transmitted in the download request message (TCODE 18)
will always be the MSB of the register referenced by the opcode (SC field
in the case of the RWA register).
Access Type
Updates,” for RWAR and partial register update details respectively.
MPC561/MPC563 Reference Manual, Rev. 1.2
Full RWAR
NOTE
Update
Reduced Port Mode
2 MDO / 1 MDI pins
0.28
0.25
0.27
9
Partial RWAR
Update
0.35
0.51
0.56
9
Full RWAR
Update
0.53
0.52
0.53
8 MDO / 2 MDI pins
17
Full Port Mode
Table 24-11
Freescale Semiconductor
Partial RWAR
Update
0.65
1.05
1.05
17
and