MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 109

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
B_CNRX0
EPEE
B0EPEE
VFLASH
VDDF
VSSF
ETRIG[1:2] / PCS[6:7]
A_AN0 / A_ANw / A_PQB0
A_AN1 / A_ANx/ A_PQB1
4
4
4
Signal Name
4
4
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signals
No. of
1
1
1
1
1
1
2
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Type
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
5
5
QADC64E_A and QADC64E_B
B_CNRX0
EPEE
B0EPEE
VFLASH
VDDF
VSSF
ETRIG[1:2]
A_AN0
A_AN1
Function after
Reset
UC3F Flash
1
TouCAN_B Receive Data. This signal is the serial data
input.
EPEE. This external program/erase enable control signal
externally controls the program or erase operations. When
held low, program or erase operations on the entire internal
Flash module are disabled. Available in the MPC563 only.
This signal is not connected on the MPC561.
B0EPEE. This control signal externally controls the program
or erase operations on block 0 of the internal Flash. When
held low, program or erase operations on block 0 only are
disabled. Available in the MPC563 only. This signal is not
connected on the MPC561.
VFLASH. Flash supply voltage (5-V supply) used during all
operations of the UC3F. Available in the MPC563 only. This
signal is not connected on the MPC561.
VDDF. Flash core voltage input (2.6-V supply). Available in
the MPC563 only. This signal should be connected to VDD,
preferably directly to a 2.6V plane on the circuit board. This
signal is not connected on the MPC561.
VSSF. Flash core ground reference. Available in the
MPC563 only. This signal is not connected on the MPC561.
ETRIG[1:2]. These are the external trigger inputs to the
QADC64E_A and QADC64E_B modules. ETRIG1 can be
configured to be used by both QADC64E_A and
QADC64E_B. Likewise, ETRIG2 can be used by both
QADC64E_B and QADC64E_A. The trigger input signals
are associated with the scan queues.
PCS[6:7]. This signals provide QSPI peripheral chip select
when the enhanced PCS mode is selected.
Analog Channel 0. Internally multiplexed input-only analog
channel. Passed on as a separate signal to the QADC64E.
Multiplexed Analog Input (A_ANw). Externally multiplexed
analog input.
Port A_PQB0. This is a bidirectional general-purpose I/O if
the QADC64E is configured in enhanced mode, otherwise it
is an input only.
Analog Channel 1. Internally multiplexed input-only analog
channel. Passed on as a separate signal to the QADC64E.
Multiplexed Analog Input (A_ANx). Externally multiplexed
analog input.
Port A_PQB1. This is a bidirectional general-purpose I/O if
the QADC64E is configured in enhanced mode, otherwise it
is an input only.
4
Description
Signal Descriptions
2-11