MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 254

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
6.1.4.4.1
This feature (if enabled) simplifies the masking of lower priority interrupt requests when a request of
certain priority is in service in applications that require interrupt nesting. The highest (pending) request is
also masked by itself. The masking is accomplished in the following way.
Upon asserting an interrupt request the BBC generates an acknowledge signal to notify the interrupt
controller that the request and the branch table offset have been latched. The interrupt controller then sets
a bit in the SISR register (interrupt in-service register), according to the asserted request. All other requests
whose priority is lower than or equal to the one that is currently in-service, become masked. The mask
remains set until the SISR bit is cleared by software (by the interrupt handler routine), writing a ‘1’ value
to the corresponding bit. The lower priority request masking diagram is presented in
The lower priority request masking feature is disabled by HRESET and it may be enabled by setting the
LPMASK_EN bit in the SIUMCR register.
The feature must be activated only together with exception table relocation in the BBC module.
6.1.4.4.2
The enhanced interrupt controller is a feature that may be enabled according to a user’s application using
the EICEN control bit in SIUMCR register, which can be set and cleared at any time by software. If the bit
is cleared, the default interrupt controller operation is available, as described in
Interrupt Controller Operation (MPC555/MPC556-Compatible
compatible with the interrupt controller already implemented in MPC555/MPC556.
Figure 6-5
6-14
IMPU
acknowledge
Reset by
software
SIPEND [i]
SIMASK [i]
illustrates the interrupt controller functionality in the MPC561/MPC563.
Lower Priority Request Masking
In the regular mode of the interrupt controller the lower priority request
masking feature is not available.
Backward Compatibility with MPC555/MPC556
Figure 6-4. Lower Priority Request Masking—One Bit Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Reset
Set
SISR[i]
From bit i - 1
NOTE
Enable
control bit
(LPMASK_EN)
To bit i + 1
Mode).” The regular operation is fully
Section 6.1.4.3, “Regular
To SIVEC
generation
Freescale Semiconductor
To RCPU
External
interrupt
request
generation
(OR between
all the bits)
Figure
6-4.