MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 101

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

2.2
Table 2-1
Freescale Semiconductor
ADDR[8:31] / SGPIOA[8:31]
DATA[0:31] / SGPIOD[0:31]
TSIZ[0:1]
RD/WR
BURST
BDIP
TS
TA
Signal Name
Signal Summary
describes individual MPC561/MPC563 signals, grouped by functional module.
Signals
No. of
24
32
2
1
1
1
1
1
Table 2-1. MPC561/MPC563 Signal Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Controlled by
RCW[SC].
See
Controlled by
RCW[SC].
See
TSIZ[0:1]
RD/WR
BURST
BDIP
TS
TA
Function after
Reset
Table
Table
Bus Interface
6-10.
6-10.
1
Address Bus [8:31]. Specifies the physical address of the
bus transaction. The address is driven onto the bus and kept
valid until a transfer acknowledge is received from the slave.
ADDR8 is the MSB for this bus.
Port SGPIOA[8:31]. Allows the signals to be used as
general-purpose inputs/outputs.
Data Bus [0:31]. Provides the general-purpose data path
between the MPC561/MPC563 and all other devices.
Although the data path is a maximum of 32 bits wide, it can
be sized to support 8-, 16-, or 32-bit transfers. DATA0 is the
MSB of the data bus.
Port SGPIOD[0:31]. Allows the signals to be used as
general-purpose inputs/outputs.
Transfer Size [0:1]. Indicates the size of the requested data
transfer in the current bus cycle.
Read/Write. Indicates the direction of the data transfer for a
transaction. A logic one indicates a read from a slave device;
a logic zero indicates a write to a slave device.
Burst Indicator. Driven by the bus master to indicate that the
currently initiated transaction is a burst.
Burst Data In Progress. Indicates to the slave that there is a
data beat following the current data beat.
Transfer Start. Indicates the start of a bus cycle that
transfers data to/from a slave device. This signal is driven by
the master only when it has gained ownership of the bus.
Every master should negate this signal before relinquishing
the bus.
This is an active-low signal and needs an external pull-up
resistor to ensure proper operation and meet signal timing
specifications.
Transfer Acknowledge. This line indicates that the slave
device addressed in the current transaction has accepted
the data transferred by the master (write) or has driven the
data bus with valid data (read). The slave device negates the
TA signal after the end of the transaction. The slave device
will then immediately three-state the TA signal to prevent
contention on the line in case a new transfer that addresses
another slave device(s) is initiated.
This signal is an active-low signal and needs an external
pull-up resistor to ensure proper operation and conform to
signal timing specifications.
Description
Signal Descriptions
2-3