MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 47
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Figure
Number
CCW Freeze Situation 17 ..................................................................................................... 13-63
CCW Freeze Situation 18 ..................................................................................................... 13-63
CCW Freeze Situation 19 ..................................................................................................... 13-63
External Trigger Mode (Positive Edge) Timing with Pause................................................. 13-64
Gated Mode, Single-Scan Timing ........................................................................................ 13-65
Gated Mode, Continuous Scan Timing................................................................................. 13-66
Equivalent Analog Input Circuitry ....................................................................................... 13-68
Errors Resulting from Clipping ............................................................................................ 13-69
Star-Ground at the Point of Power Supply Origin ................................................................ 13-71
Electrical Model of an A/D Input Signal .............................................................................. 13-72
External Multiplexing of Analog Signal Sources ................................................................. 13-74
Input Signal Subjected to Negative Stress ............................................................................ 13-76
Input Signal Subjected to Positive Stress ............................................................................. 13-77
QADC64E Block Diagram ..................................................................................................... 14-1
CCW Queue and Result Table Block Diagram ...................................................................... 14-5
Example of External Multiplexing ......................................................................................... 14-6
Module Configuration Register (QADCMCR) ...................................................................... 14-8
QADC Interrupt Register (QADCINT) ................................................................................ 14-12
Interrupt Levels on IRQ with ILBS ...................................................................................... 14-12
Port A Data Register (PORTQA), Port B Data Register (PORTQB)................................... 14-13
Control Register 0 (QACR0) ................................................................................................ 14-14
Control Register 2 (QACR2) ................................................................................................ 14-18
Status Register 0 (QASR0) ................................................................................................... 14-22
Queue Status Transition........................................................................................................ 14-27
Status Register 1 (QASR1) ................................................................................................... 14-28
QADC64E Conversion Queue Operation............................................................................. 14-29
Conversion Command Word Table (CCW) ......................................................................... 14-31
Right Justified, Unsigned Result Format (RJURR).............................................................. 14-35
Left Justified, Signed Result Format (LJSRR) ..................................................................... 14-35
Left Justified, Unsigned Result Register (LJURR) .............................................................. 14-35
QADC64E Analog Subsystem Block Diagram .................................................................... 14-36
Conversion Timing ............................................................................................................... 14-37
QADC64E Queue Operation With Pause ............................................................................. 14-40
QADC64E Clock Subsystem Functions ............................................................................... 14-49
Bus Cycle Accesses .............................................................................................................. 14-52
CCW Priority Situation 1...................................................................................................... 14-55
CCW Priority Situation 2...................................................................................................... 14-55
CCW Priority Situation 3...................................................................................................... 14-56
Port
Control Register 1 (QACR1) ............................................................................................... 14-16
x
Data Direction Register (DDRQA and DDRQB) ...................................................... 14-14
MPC561/MPC563 Reference Manual, Rev. 1.2
Figures
Title
Number
Page
xlvii
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