MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 15

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

12.4.1
12.4.2
12.4.3
12.4.4
12.5
12.5.1
12.5.2
12.5.3
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.1.3
13.3.1.4
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.3.10
13.4
13.4.1
13.4.1.1
13.4.1.2
13.4.2
13.4.3
13.4.4
Freescale Semiconductor
Paragraph
Number
Programming Model ..................................................................................................... 12-6
QADC64E Block Diagram ........................................................................................... 13-1
Key Features and Quick Reference Diagrams .............................................................. 13-2
Programming the QADC64E Registers ........................................................................ 13-7
Analog Subsystem ...................................................................................................... 13-34
Interrupt Sources and Levels on IMB3 ..................................................................... 12-3
IMB3 Interrupt Multiplexing .................................................................................... 12-4
ILBS Sequencing ...................................................................................................... 12-4
Interrupt Synchronizer .............................................................................................. 12-5
UIMB Module Configuration Register (UMCR) ..................................................... 12-7
Test Control Register (UTSTCREG) ........................................................................ 12-8
Pending Interrupt Request Register (UIPEND) ........................................................ 12-8
Features of the QADC64E Legacy Mode Operation ................................................ 13-2
Memory Map ............................................................................................................ 13-3
Legacy and Enhanced Modes of Operation .............................................................. 13-4
Using the Queue and Result Word Table ................................................................. 13-5
External Multiplexing ............................................................................................... 13-5
QADC64E Module Configuration Register (QADMCR) ........................................ 13-8
QADC64E Interrupt Register (QADCINT) ............................................................ 13-12
Port Data Register (PORTQA and PORTQB) ........................................................ 13-13
Port Data Direction Register (DDRQA) ................................................................. 13-14
Control Register 0 (QACR0) .................................................................................. 13-14
Control Register 1 (QACR1) .................................................................................. 13-15
Control Register 2 (QACR2) .................................................................................. 13-17
Status Registers (QASR0 and QASR1) .................................................................. 13-20
Conversion Command Word Table ........................................................................ 13-27
Result Word Table .................................................................................................. 13-32
Analog-to-Digital Converter Operation .................................................................. 13-34
Channel Decode and Multiplexer ........................................................................... 13-36
Sample Buffer Amplifier ........................................................................................ 13-36
Digital-to-Analog Converter (DAC) Array ............................................................ 13-36
Low Power Stop Mode ......................................................................................... 13-9
Freeze Mode ......................................................................................................... 13-9
Switching Between Legacy and Enhanced Modes of Operation ........................ 13-10
Supervisor/Unrestricted Address Space ............................................................. 13-10
Conversion Cycle Times ..................................................................................... 13-35
Amplifier Bypass Mode Conversion Timing ..................................................... 13-35
QADC64E Legacy Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Chapter 13
Title
Number
Page
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