MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1049

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

24.14.2.4 RCPU Development Access Flow Diagram
Figure 24-83
signals.
Freescale Semiconductor
DEBUG MODE NOT ENALBED
*(exit loop via READI reset (*A*)
or system reset (*B*))
(synch.self-clk mode)
Device sends DSDO Message
Tool sends DSDI Message
*A*
*B*
has flow diagram describing how the RCPU development access can be achieved via READI
(@ subsequent READI reset)
DSDI=1
(@ subsequent RCPU reset)
(DME=0)
Figure 24-83. RCPU Development Access Flow Diagram
DSCK=0 within 8 clocks of SRESET
(Debug Mode not enabled) No
negation to NOT enter debug mode
DSDI=1 (sync. self-clk mode)
MPC561/MPC563 Reference Manual, Rev. 1.2
(No Debug out-of-reset) No
Tools Negates HRESET 16 clocks after receiving Device Ready
Tool sends Download Request Message and configures
*(exit loop via
READI reset
(*A*) or via
system reset
(*B*))
READI module (assign DPA, DME & DOR, etc.)
(DPA, DME, DOR, etc. bits locked)
Tool Asserts and Negates RSTI
DEBUG MODE ENABLED
Device sends DID message
No
No
Entry?
BDM
Exit?
BDM
Device sends DSDO Message
Tool sends DSDI Message
Tool Asserts HRESET
DME=1
DOR=1
(DME=1)
Device sends Debug Mode Status
?
?
Yes
Yes (Debug Mode enabled)
Yes
DSCK=1 until 16 clocks after SRESET
“BDM entry” (status bit = 1)
Device sends Debug Mode
“BDM exit” (status bit = 0)
negation to enter debug mode
DSDI=1 (sync. self-clk mode)
Status Message
Yes (Debug out-of-reset)
Message
READI Module
24-81