MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 303
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 8
Clocks and Power Control
The main timing reference for the MPC561/MPC563 can monitor any of the following:
The system operating frequency is generated through a programmable phase-locked loop, the system PLL
(SPLL). The SPLL runs at twice the system speed. The SPLL is programmable in integer multiples of the
input frequency to generate the internal (VCO/2) operating frequency. A pre-divider before the SPLL
enables the division of the high frequency crystal oscillator. The internal operating SPLL frequency should
be at least 30 MHz. It can be divided by a power-of-two divider to generate the system operating
frequencies.
In addition to the system clock, the clocks submodule provides the following:
The oscillator, TB, DEC, RTC, and the PIT are powered from the keep alive power supply (KAPWR) pin.
This allows the counters to continue to increment/decrement at the oscillator frequency even when the
main power to the MCU is off. While the power is off, the PIT may be used to signal the power supply IC
to enable power to the system at specific intervals. This is the power-down wake-up feature. When the chip
is not in power-down low-power mode, the KAPWR is powered to the same voltage value as the voltage
of the I/O buffers and logic.
The MPC561/MPC563 clock module consists of the main crystal oscillator, the SPLL, the low-power
divider, the clock generator, the system low-power control block, and the limp mode control block. The
clock module receives control bits from the system clock control register (SCCR), change of lock interrupt
register (COLIR), the PLL low-power and reset-control register (PLPRCR), and the PLL.
Freescale Semiconductor
•
•
•
•
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An external crystal with a frequency of 4 or 20 MHz
An external frequency source with a frequency of 4 MHz
An external frequency source at the system frequency
TMBCLK to the time base (TB) and decrementer (DEC)
PITRTCLK to the periodic interrupt timer (PIT) and real-time clock (RTC)
MPC561/MPC563 Reference Manual, Rev. 1.2
8-1
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