MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 308
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
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Clocks and Power Control
8.3
At reset, until the SPLL is locked, the SPLL output clock is disabled.
During normal operation (once the PLL has locked), either the oscillator or an external clock source is
generating the system clock. In this case, if loss of lock is detected and the LOLRE (loss of lock reset
enable) bit in the PLPRCR is cleared, the system clock source continues to function as the PLL’s output
clock. The USIU timers can operate with the input clock to the PLL, so that these timers are not affected
by the PLL loss of lock. Software can use these timers to measure the loss-of-lock period. If the timer
reaches the user-preset software criterion, the MPC561/MPC563 can switch to the backup clock by setting
the switch to backup clock (STBUC) bit in the SCCR, provided the limp mode enable (LME) bit in the
SCCR is set.
If loss of lock is detected during normal operation, assertion of HRESET (for example, if LOLRE is set)
disables the PLL output clock until the lock condition is met. During hard reset, the STBUC bit is set as
long as the PLL lock condition is not met and clears when the PLL is locked. If STBUC and LME are both
set, the system clock switches to the backup clock (BUCLK), and the chip operates in limp mode until
STBUC is cleared.
Every change in the lock status of the PLL can generate a maskable interrupt.
8.4
The output of the PLL is sent to a low-power divider block. (In limp mode the BUCLK is sent to a
low-power divider block.) This block generates all other clocks in normal operation, but has the ability to
divide the output frequency of the VCO before it generates the general system clocks sent to the rest of the
MPC561/MPC563. The PLL VCOOUT is always divided by at least two.
The purpose of the low-power divider block is to allow reduction and restoration of the operating
frequencies of different sections of the MPC561/MPC563 without losing the PLL lock. Using the
low-power divider block, full chip operation can still be obtained, but at a lower frequency. This is called
gear mode. The selection and speed of gear mode can be changed at any time, with changes occurring
immediately.
8-6
•
XFC — External filter capacitor. XFC connects to the off-chip capacitor for the PLL filter. One
terminal of the capacitor is connected to XFC, and the other terminal is connected to VDDSYN.
— The off-chip capacitor must have the following values:
System Clock During PLL Loss of Lock
Low-Power Divider
– 0 < MF + 1 < 4 (1130
– MF + 1 ≥ 42100
Where MF = the value stored on MF[0:11]. This is one less than the desired
frequency multiplication.
When the VCO is the system clock source, chip operation is unpredictable
while the PLL is unlocked. Note further that a switch to the backup clock is
possible only if the LME bit in the SCCR is set.
x
(MF + 1) pF
MPC561/MPC563 Reference Manual, Rev. 1.2
x
(MF + 1) – 80) pF
NOTE
Freescale Semiconductor
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