MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1009

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
At Time 11, the Indirect Branch is mispredicted taken.
At Time 15, branch correction occurs due to the mispredicted branch which was taken at Time 11. A
program trace correction message is sent out correcting the number of instructions in the trace (1).
Sequential instruction which occurred at Time 12, 13, and 14 respectively are not included in the
correction count because the tool is not aware that they occurred (they were not transmitted out).
At Time 18, the Indirect Branch Message indicates that 3 sequential instructions were executed since
trace correction (this includes the mispredicted branch instruction which is considered to be a
sequential instruction).
Table 24-27. Program Trace Correction Due to a Mispredicted Branch (continued)
Time
14
15
16
17
18
Time
10
11
1
2
3
4
5
6
7
8
9
Table 24-28. Program Trace Correction Due to an Exception
Indirect Branch Instruction
Indirect Branch Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Direct Branch Instruction
Branch Correction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Processor State
(predicted taken)
MPC561/MPC563 Reference Manual, Rev. 1.2
Processor State
Program Trace Correction Message
TCODE = 10
Number of instructions to rewind from trace = 1
Indirect Branch Message
TCODE = 4
Number of sequential instructions executed
since last valid taken branch = 3
Unique portion of the target address
Direct Branch Message
Indirect Branch Message
TCODE = 3
Number of sequential instructions executed
since last taken branch = 3
TCODE = 4
Number of sequential instructions executed
since last taken branch = 4
Unique portion of the target address
Message sent
Message sent
READI Module
24-41