MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 478

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
13.3.4
The port data direction register, DDRQA, is associated with port A digital input/output signals only. Any
bit set in this register configures the corresponding signal as an output. Any bit cleared in this register
configures the corresponding signal as an input. The software is responsible for ensuring that DDR bits are
not set on signals used for analog inputs. When the DDR bit is set, thereby selecting the signal for analog
conversion, the voltage sampled is that of the output digital driver as influenced by the load.
There are two special cases to consider for the digital I/O port operation. When QACR0[EMUX] is set,
enabling external multiplexing, the data direction register settings are ignored for the bits corresponding
to PORTQA[2:0], which are the three multiplexed address (MA[2:0]) output signals. The MA[2:0] signals
are forced to be digital outputs, regardless of the data direction setting, and the multiplexed address outputs
are driven. The data returned during a port data register read is the value of the multiplexed address latches
which drive MA[2:0], regardless of the data direction setting.
13.3.5
Control Register 0 is used to define whether external multiplexing is enabled, assign external triggers to
the conversion queues and to sets up the QCLK prescaler parameter field. All of the implemented control
13-14
MULTIPLEXED ANALOG INPUTS:
SRESET
Bits
8:15
0:7
Field DDQ
Addr
PQA[7:0]
Port Data Direction Register (DDRQA)
Control Register 0 (QACR0)
PQB[7:0]
Name
MSB
A7
Caution should be exercised when mixing digital and analog inputs. This
should be isolated as much as possible. Rise and fall times should be as large
as possible to minimize AC coupling effects.
0
DDQ
A6
1
Port A signals are referred to as PQA when used as an 8-bit input/output port. Port A can also
be used for analog inputs (AN[59:52]), and external multiplexer address outputs (MA[2:0]).
Port B signals are referred to as PQB when used as an 8 input-only port. Port B can also be used
for non-multiplexed (AN[51:48]/AN[3:0]) and multiplexed (ANz, ANy, ANx, ANw) analog inputs.
Figure 13-7. Port x Data Register (PORTQA and PORTQB)
DDQ
Figure 13-8. Port A Data Direction Register (DDRQA)
A5
2
Table 13-8. PORTQA, PORTQB Bit Descriptions
DDQ
A4
MPC561/MPC563 Reference Manual, Rev. 1.2
3
0x30 4808 (DDRQA_A); 0x30 4C08 (DDRQA_B)
DDQ
A3
4
DDQ
A2
5
0000_0000_0000_0000
NOTE
DDQ
A1
6
DDQ
A0
Description
7
8
9
10
11
—
ANz
12
Freescale Semiconductor
ANy
13
ANx ANw
14
LSB
15