MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 169

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

3.9.9
The PVR is a 32-bit, read-only register that identifies the version and revision level of the processor. The
contents of the PVR can be copied to a GPR by the mfspr instruction. Read access to the PVR is available
in supervisor mode only; write access is not provided.
3.9.10
The MPC561/MPC563 includes several implementation-specific SPRs that are not defined by the
PowerPC ISA architecture. These registers, listed in
supervisor-level instructions only.
3.9.10.1
The RCPU includes three implementation-specific SPRs that facilitate the software manipulation of the
MSR[RI] and MSR[EE] bits: External Interrupt Enable (EIE), External Interrupt Disable (EID), and
Non-recoverable Interrupt (NRI). Issuing the mtspr instruction with one of these registers as an operand
causes the RI and EE bits to be set or cleared as shown in
A read (mfspr) of any of these locations is treated as an unimplemented instruction, resulting in a software
emulation exception.
Freescale Semiconductor
16:31
Bits
0:15
Reset
Field
Addr
Processor Version Register (PVR)
Implementation-Specific SPRs
MSB
EIE, EID, and NRI Special-Purpose Registers
0
REVISION
VERSION
Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
0000_0000_0000_0010
Table 3-14. Processor Version Register Bit Descriptions
A 16-bit number that identifies the version of the PowerPC ISA processor. The RCPU value
is 0x0002.
A 16-bit number that distinguishes between various releases of a particular version. The
RCPU value is 0x0020.
VERSION
Figure 3-17. Processor Version Register (PVR)
SPR Number
(Decimal)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-15. EIE, EID, AND NRI Registers
80
81
82
Mnemonic
EID
NRI
EIE
Table 3-2
SPR 287
MSR[EE]
Table
Description
1
0
0
and
3-15.
Table
MSR[RI]
0000_0000_0010_0000
1
1
0
3-3, can be accessed by
REVISION
Central Processing Unit
LSB
31
3-25