MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1215

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Note: L = L-bus, U = U-bus, E = E-bus, C = CMF (Flash), IMB = intermodule bus, DC = DECRAM
Note: Shaded areas = address phase ; Non-shaded areas = data phase
Freescale Semiconductor
1
2
3
4
Instruction Fetch->
cmf
2 consecutive
accesses and
External Bus-> cmf
N is the number of read cycle clocks from external address valid until external data valid. In the case of zero wait states,
N = 2.
Core instruction fetch data bus is usually the U-bus
8 clocks are dedicated for external accesses, and internal accesses are denied.
Assuming the external master immediately retries
Access
Table E-2. Instruction Timing Examples for Different Buses (continued)
E
1
C,U
2
Retr
MPC561/MPC563 Reference Manual, Rev. 1.2
U
C
3
y
—
E
4
4
3
—
5
Number of Clocks
—
U
6
—
U
7
—
E
8
—
9
10
—
11
—
12
U
Memory Access Timing
13
U
Total
11
2
8
E-3