MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 402

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Memory Controller
When a match is found on one of the memory banks, its attributes are selected for the functional operation
of the external memory access:
Note that if more than one region matches the internal address supplied, then the lowest numbered region
is selected to provide the attributes and the chip select. If the dual mapping region is matched, it has the
highest priority (refer to
10.2.1
Status bits for each memory bank are found in the memory control status register (MSTAT). The MSTAT
reports write-protect violations for all the banks.
Each of the four memory banks has a base register (BR) and an option register (OR). The BRx and ORx
registers contain the attributes specific to memory bank x. The base register contains a valid bit (V) that
indicates the register information for that particular chip select is valid.
10.2.2
The memory controller supports dynamic bus sizing. Defined 8-bit ports can be accessed as odd or even
bytes. Defined 16-bit ports, when connected to data bus lines zero to 15, can be accessed as odd bytes, even
bytes, or even half-words. Defined 32-bit ports can be accessed as odd bytes, even bytes, odd half-words,
even half-words, or words on word boundaries. The port size is specified by the PS bits in the base register.
10-4
•
•
•
•
A[0:16]
Read-only or read/write operations
Number of wait states for a single memory access, and for any beat in a burst access
Burst-inhibit indication. Internal burst requests are still possible during burst-inhibited cycles; the
memory controller emulates the burst cycles
Port size of the external device
cmp cmp cmp cmp cmpcmpcmp
Associated Registers
Port Size Configuration
Base Address
Section 10.5, “Dual Mapping of the Internal Flash EEPROM
Figure 10-4. Bank Base Address and Match Structure
. . . . . . . . . . . . .
MPC561/MPC563 Reference Manual, Rev. 1.2
cmp
cmp cmp cmp
M0 M1 M2 M3 M4 M5
M[0:16]
Address Mask
Match
M6 M7
Freescale Semiconductor
Array”).
. . . .
M16