MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 634

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
A dedicated 160-byte RAM is used to store received data, data to be transmitted, and a queue of
commands. The CPU can access these locations directly. This allows serial peripherals to be treated like
memory-mapped parallel devices.
The command queue allows the QSPI to perform up to 32 serial transfers without CPU intervention. Each
queue entry contains all the information needed by the QSPI to independently complete one serial transfer.
A pointer identifies the queue location containing the data and command for the next serial transfer.
Normally, the pointer address is incremented after each serial transfer, but the CPU can change the pointer
value at any time. Support for multiple-tasks can be provided by segmenting the queue.
The QSPI has four peripheral chip-select pins. The chip-select signals simplify interfacing by reducing
CPU intervention. If the chip-select signals are externally decoded, 16 independent select signals can be
generated.
Wrap-around mode allows continuous execution of queued commands. In wraparound mode, newly
received data replaces previously received data in the receive RAM. Wrap-around mode can simplify the
interface with A/D converters by continuously updating conversion values stored in the RAM.
Continuous transfer mode allows transfer of an uninterrupted bit stream. From 8 to 512 bits can be
transferred without CPU intervention. Longer transfers are possible, but minimal intervention is required
to prevent loss of data. A standard delay of 17 IMB3 clocks (0.8 µs with a 40-MHz IMB3 clock) is inserted
between the transfer of each queue entry.
15.6.1
The QSPI memory map, shown in
QSPI control registers (SPCR[0:3]), the status register (SPSR), and the QSPI RAM. Registers and RAM
can be read and written by the CPU. The memory map can be divided into supervisor-only data space and
assignable data space. The address offsets shown are from the base address of the QSMCM module. Refer
to
15-16
Figure 1-4
Access
S/U
S/U
S/U
S/U
S/U
1
QSPI Registers
for a diagram of the MPC561/MPC563 internal memory map.
0x30 5140 –
0x30 501E/
0x30 501A
0x30 501C
0x30 5018
0x30 501F
0x30 517F
Address
MSB
0
See <XrefBlue>Table 15-17 for bit descrip-
2
QSPI Control Register 3 (SPCR3)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
Table 15-12. QSPI Register Map
15-12, includes the QSMCM global and pin control registers, four
tions.
See <XrefBlue>Table 15-13 for bit descriptions.
See <XrefBlue>Table 15-15 for bit descriptions.
See <XrefBlue>Table 15-16 for bit descriptions.
Receive Data RAM (32 half-words)
QSPI Control Register 0 (SPCR0)
QSPI Control Register 1 (SPCR1)
QSPI Control Register 2 (SPCR2)
See <XrefBlue>Table 15-18 for bit descrip-
QSPI Status Register (SPSR)
tions.
Freescale Semiconductor
LSB
15