MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 541
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The current into the signal (I
equations:
where:
The current into (I
parasitic bipolar transistor (K
where I
A method for minimizing the impact of stress conditions on the QADC64E is to strategically allocate
QADC64E inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress
conditions.
Also, suitable source impedances should be selected to meet design goals and minimize the effect of stress
conditions.
Freescale Semiconductor
INJ
is either I
V
V
(refer to V
V
(refer to V
R
(10-kΩ resistor in
R
I
IN
STRESS
SELECTED
STRESS
EB
BE
= - K
IN
= Parasitic NPN base/emitter voltage
= Parasitic PNP emitter/base voltage
) the neighboring signal is determined by the K
INJN
= Source impedance
= Adjustable voltage source
N
NEGCLAMP
NEGCLAMP
or I
= Source impedance on channel selected for conversion
* I
Figure 13-55. Input Signal Subjected to Positive Stress
INJ
INJP
INJN
N
V
<< 1). The I
.
IN
or I
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 13-54
V
I INJP
in
in
STRESS
I INJN
INJP
Appendix F, “Electrical
Appendix F, “Electrical
+
) under negative or positive stress is determined by the following
=
=
V STRESS V EB
--------------------------------------------------------------------- -
–
----------------------------------------------------- -
IN
R
(
V STRESS V BE
SELECTED
R
can be expressed by the following equation:
and
STRESS
R STRESS
10K
R STRESS
Figure 13-55
–
I
INJP
I
–
IN
PARASITIC
–
DEVICE
AN
AN
V DDA
)
n+1
n
Characteristics”)
Characteristics”)
Signal Under
Adjacent
on stressed channel)
Stress
signal
N
(current coupling ratio) of the
V
DDA
QADC64E Legacy Mode Operation
QADC64E PAR
Eqn. 13-2
Eqn. 13-3
13-77
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