MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 219

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

4.4.1
In the case of decompression off mode, the DECRAM can serve as a two-clock access general-purpose
RAM for U-bus instruction fetches or four-clock access for read/write data operations. The base address
of the DECRAM is 0x2F 8000. See
defined by programming the R, D, and S bits of the BBCMCR register:
Freescale Semiconductor
•
•
•
ICDU
VT1 Address
Read/write or read only
Instruction/data or data only
Supervisor/user or supervisor only
General-Purpose Memory Operation
U-bus Data
Vocabulary Table (VT1)
Array
Figure 4-4. DECRAM Interfaces Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
(1 Kbyte)
Figure
VT1 Data
ICDU Control Logic
4-6. The proper access rights to the DECRAM array may be
VT2 Address
DECRAM
Slave BIU
Vocabulary Table (VT2)
Array
U-bus Address
(1 Kbyte)
Burst Buffer Controller 2 Module
VT2 Data
4-13