MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1008

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

READI Module
24.8.2.3
In case of a mispredicted branch or an exception, a program trace correction message may also be sent
indicating a number which corrects the number of instructions (not messages) in the trace.
In the case of a synchronizing branch trace message getting corrected due to a misprediction or an
exception, the next branch trace message will be a synchronizing message.
Table 24-27
Table 24-28
24-40
illustrates an example of a program trace correction message in case of a mispredicted branch.
illustrates an example of a program trace correction message in case of an exception.
Correction Messages
Time
In case of a mispredicted branch, the correction count is always 1 and the
sequential instruction count is reset to 1 (to denote the not-taken branch as
a sequential instruction), after the program trace correction message is sent.
This is because a mispredicted branch is considered to be a sequential
instruction.
In case of an exception, the sequential instruction count is reset to 0, after
the program trace correction message is sent.
10
11
12
13
1
2
3
4
5
6
7
8
9
Table 24-27. Program Trace Correction Due to a Mispredicted Branch
Indirect Branch Instruction
Direct Branch Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
Sequential Instruction
(mispredicted taken)
Processor State
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
NOTE
Direct Branch Message
TCODE = 3
Number of sequential instructions executed
since last taken branch = 5
Indirect Branch Message
TCODE = 4
Number of sequential instructions executed
since last taken branch = 4
Unique portion of the target address
Message sent
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