MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 372

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

External Bus Interface
Table 9-3
access.
Note: “—” denotes a byte not driven during that write cycle.
9.5.7
The external bus design provides for a single bus master at any one time, either the MPC561/MPC563 or
an external device. One or more of the external devices on the bus can have the capability of becoming bus
master for the external bus. Bus arbitration may be handled either by an external central bus arbiter or by
the internal on-chip arbiter. In the latter case, the system is optimized for one external bus master besides
the MPC561/MPC563. The arbitration configuration (external or internal) is set at system reset.
Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. The device that
needs the bus asserts BR. The device then waits for the arbiter to assert BG. In addition, the new master
must look at BB to ensure that no other master is driving the bus before it can assert BB to assume
ownership of the bus. Any time the arbiter has taken the bus grant away from the master and the master
wants to execute a new cycle, the master must re-arbitrate before a new cycle can be executed. The
MPC561/MPC563, however, guarantees data coherency for access to a small port size and for decomposed
bursts. This means that the MPC561/MPC563 will not release the bus before the completion of the
transactions that are considered atomic.
9-32
lists the patterns of the data transfer for write cycles when the MPC561/MPC563 initiates an
Arbitration Phase
Half-word
Transfer
Word
Size
Byte
TSIZE[0:1]
01
01
01
01
10
10
00
Table 9-3. Data Bus Contents for Write Cycles
MPC561/MPC563 Reference Manual, Rev. 1.2
Address
[30:31]
ADDR
00
01
10
11
00
10
00
Figure 9-24
DATA
[0:7]
OP0
OP1
OP2
OP3
OP0
OP2
OP0
describes the basic protocol for bus arbitration.
External Data Bus Pattern
[8:15]
DATA
OP1
OP3
OP1
OP3
OP1
—
—
[16:23]
DATA
OP2
OP2
OP2
—
—
—
—
Freescale Semiconductor
[24:31]
DATA
OP3
OP3
OP3
—
—
—
—