MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 550

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Enhanced Mode Operation
14.3.1
The QADCMCR contains fields and bits that control freeze and stop modes, operating mode of the
QADC64E module, determine the privilege level required to access most registers and master/slave
operation.
14.3.1.1
When the STOP bit in the QADCMCR is set, the QADC64E clock (QCLK) which clocks the A/D
converter, is disabled and the analog circuitry is powered down. This results in a static, low power
consumption, idle condition. The stop mode aborts any conversion sequence in progress. Because the bias
currents to the analog circuits are turned off in stop mode, the QADC64E requires some recovery time (T
in Appendix F: Electricl Characteristics) to stabilize the analog circuits after the stop enable bit is cleared.
14-8
.
SRESET
Bits
9:15
2:5
0
1
6
7
8
Field STOP FRZ
Addr
QADC64E Module Configuration Register
MSB
Low Power Stop Mode
Name
STOP
LOCK
SUPV
0
FLIP
FRZ
—
—
1
Stop Enable. Refer to
0 Disable stop mode
1 Enable stop mode
Freeze Enable. Refer to
0 Ignores the IMB3 internal FREEZE signal
1 Finish any conversion in progress, then freeze
Reserved
Lock/Unlock QADC Mode of operation as defined by FLIP bit. Refer to
“Switching Between Legacy and Enhanced Modes of
0 QADC mode is locked
1 QADC mode is unlocked and changeable using FLIP bit
QADC Mode of Operation. The FLIP bit allows selection of the mode of operation of the QADC
module, either Legacy Mode (default) or Enhanced Mode. This bit can only be written when the
LOCK is set (unlocked). Refer to
Modes of
0 Legacy Mode enabled
1 Enhanced Mode enabled
Supervisor/Unrestricted Data Space. Refer to
Address
0 Only the module configuration register, test register, and interrupt register are designated as
1 All QADC64E registers and CCW/result tables are designated as supervisor-only data space.
Reserved.
Figure 14-4. Module Configuration Register (QADCMCR)
supervisor-only data space. Access to all other locations is unrestricted.
2
0000_0000
Space” and
Operation” for more information.
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 14-5. QADCMCR Bit Descriptions
—
0x30 4800 (QADCMCR_A); 0x30 4C00 (QADCMCR_B)
4
Table 14-6
Section 14.3.1.1, “Low Power Stop
5
Section 14.3.1.2, “Freeze
LOCK FLIP SUPV
6
for more information.
Section 14.3.1.3, “Switching Between Legacy and Enhanced
7
Description
1
8
Section 14.3.1.4, “Supervisor/Unrestricted
Mode” for more information.
9
Operation” for more information.
Mode” for more information.
10
11
000_0000
Section 14.3.1.3,
—
12
Freescale Semiconductor
13
14
LSB
15
SR