MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 756

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Modular Input/Output Subsystem (MIOS14)
17.8.5.3
17.8.5.4
The MMCSMSCRD and the MMCSMSCR are the same registers accessed at two different addresses.
Reading or writing to one of these two addresses has exactly the same effect.
The duplication of the SCR register allows coherent 32-bit accesses when using a RCPU.
17.8.5.5
The status/control register (SCR) is a collection of read-only signal status bits, read/write control bits and
an 8-bit read/write data register, as detailed below.
17-24
SRESET
SRESET
Bits
0:15
Field PINC
Addr
Field
Addr
MSB
MSB
0
MMCSM Modulus Latch Register (MMCSMML)
MMCSM Status/Control Register (MMCSMSCRD)
(Duplicated)
MMCSM Status/Control Register (MMCSMSCR)
Name
0
The user should not write directly to the address of the MMCSMSCRD.
This register’s address may be reserved for future use and should not be
accessed by the software to ensure future software compatibility.
ML
PINL FREN EDGN EDGP
1
1
Modulus latches — These bits are read/write data bits containing the 16-bit modulus value to be
loaded into the up-counter.
The value loaded in this register must be the one’s complement of the desired modulus count.
The up-counter increments from this one’s complement value up to 0xFFFF to get the correct
number of steps before an overflow is generated to reload the modulus value into the up-counter.
Figure 17-14. MMCSM Status/Control Register (MMCSMSCR)
Figure 17-13. MMCSM Modulus Latch Register (MMCSMML)
2
2
0x30 6032, 0x30 603A, 0x30 6042, 0x30 60B2, 0x30 60BA, 0x30 60C2
0x30 6036, 0x30 603E, 0x30 6046, 0x30 60B6, 0x30 60BE, 0x30 60C6
3
3
Table 17-11. MMCSMML Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
4
4
5
5
WARNING
CLS
6
6
Undefined
Undefined
7
ML
Description
—
7
8
8
9
9
10
10
11
11
CP
12
Freescale Semiconductor
12
13
13
14
14
LSB
15
LSB
15