MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 925

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

23.2.1.1
There are cases when the same watchpoint can be detected more than once during the execution of a single
instruction, e.g. a load/store watchpoint is detected on more than one transfer when executing a load/store
multiple/string or a load/store watchpoint is detected on more than one byte when working in byte mode.
In all these cases only one watchpoint of the same type is reported for a single instruction. Similarly, only
one watchpoint of the same type can be counted in the counters for a single instruction.
Because watchpoint events are reported upon the retirement of the instruction that caused the event, and
more than one instruction can retire from the machine in one clock, consequent events may be reported in
the same clock. Moreover the same event, if detected on more than one instruction (e.g., tight loops, range
detection), in some cases will be reported only once. Note that the internal counters count correctly in these
cases.
Do not put a breakpoint on an mtspr instruction that accesses the ICTRL register when ICTRL[IFM] = 1
because this causes unpredictable behavior.
23.2.1.2
The CPU watchpoints and breakpoints support enables detection of matches on bytes and half-words even
when accessed using a load/store instruction of larger data widths, for example when loading a table of
bytes using a series of load word instructions. In order to use this feature, program the byte mask for each
of the L-data comparators and to write the needed match value to the correct half-word of the data
Freescale Semiconductor
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On the fly trap enable programming of the different internal breakpoints using the serial interface
of the development port (refer to
available.
Watchpoints do not change the timing of the machine
Internal breakpoints and watchpoints are detected on the instruction during instruction fetch
Internal breakpoints and watchpoints are detected on the load/store during load/store bus cycles
Both instruction and load/store breakpoints and watchpoints are handled and reported on
retirement. Breakpoints and watchpoints on recovered instructions (as a result of exceptions,
interrupts or miss prediction) are not reported and do not change the timing of the machine.
Instructions with instruction breakpoints are not executed. The machine branches to the breakpoint
exception routine BEFORE it executes the instruction.
Instructions with load/store breakpoints are executed. The machine branches to the breakpoint
exception routine AFTER it executes the instruction. The address of the access is placed in the
BAR (breakpoint address register).
Load/store multiple and string instructions with load/store breakpoints first finish execution (all of
it) and then the machine branches to the breakpoint exception routine.
Load/store data compare is done on the load/store, AFTER swap in store accesses and BEFORE
swap in load accesses (as the data appears on the bus).
Internal breakpoints may operate either in masked mode or in non-masked mode.
Both “go to x” and “continue” working modes are supported for the instruction breakpoints.
Restrictions
Byte and Half-Word Working Modes
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 23.4, “Development
Port”). Software control is also
Development Support
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