MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1157

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

D.3
QOM can generate single- or multiple-output match events from a table of offsets in parameter RAM.
Loop modes allow complex pulse trains to be generated once, a specified number of times, or continuously.
QOM can be used with other TPU3 channels in a variety of ways: the function can be triggered by a link
from the channel, the reference time for the sequence of matches can be obtained from it, or the channel
can be used as a discrete output pin. QOM can generate pulse-width modulated waveforms, including
waveforms with high times of 0 or 100%. See Freescale TPU3 Progamming Note Queued Output Match
TPU Function (QOM), (TPUPN01/D).
Figure D-3
Table D-2
Freescale Semiconductor
Queued Output Match TPU3 Function (QOM)
describe the corresponding fields in parameter RAM.
shows all of the host interface areas for the QOM function. The bit encodings shown in
B:C
00
01
10
11
MPC561/MPC563 Reference Manual, Rev. 1.2
A
0
1
0
1
Table D-2. QOM Bit Encoding
Use TCR1 as Timebase
Use TCR2 as Timebase
Falling Edge at Match
Rising Edge at Match
Immediate TCR Value
Last Event Time
Value Pointed to by REF_ADDR
Last Event Time
Figure D-2. PTA Parameters
CONTROL BITS
Reference for First Match
Timebase Selection
Edge Selection
PRAM Address Offset Map.
See
Table 19-24
for the
TPU3 ROM Functions
D-5