MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 710

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CAN 2.0B Controller Module
16.4.4.1
Any write access to the control/status word of a receive message buffer during the process of selecting a
message buffer for reception immediately deactivates that message buffer, removing it from the reception
process.
If a receive message buffer is deactivated while a message is being transferred into it, the transfer is halted
and no interrupt is requested. If this occurs, that receive message buffer may contain mixed data from two
different frames.
The CPU should not write data into a receive message buffer. If this occurs while a message is being
transferred from a serial message buffer, the control/status word will reflect a full or overrun condition, but
no interrupt is requested.
16.4.4.2
The lock/release/busy mechanism is designed to guarantee data coherency during the receive process. The
following examples demonstrate how the lock/release/busy mechanism affects TouCAN operation:
Polling the control/status word of a receive message buffer can lock it, preventing a message from being
transferred into that buffer. If the control/status word of a receive message buffer is read, it should be
followed by a read of the control/status word of another buffer, or by a read of the free-running timer, to
ensure that the locked buffer is unlocked.
16-16
1. Reading a control/status word of a message buffer triggers a lock for that message buffer. A new
2. To release a locked message buffer, the CPU either locks another message buffer by reading its
3. If a receive frame with a matching ID is received during the time the message buffer is locked, the
4. When a locked message buffer is released, if a frame with a matching identifier exists within the
5. If two or more receive frames with matching IDs are received while a message buffer with a
6. If the control/status word of a receive message buffer is read while a frame is being transferred
received message frame which matches the message buffer cannot be written into this message
buffer while it is locked.
control/status word or globally releases any locked message buffer by reading the free-running
timer.
receive frame is not immediately transferred into that message buffer, but remains in the serial
message buffer. There is no indication when this occurs.
serial message buffer, then this frame is transferred to the matching message buffer.
matching ID is locked, the last received frame with that ID is kept within the serial message buffer,
while all preceding ones are lost. There is no indication when this occurs.
from a serial message buffer, the BUSY code is indicated. The user should wait until this code is
cleared before continuing to read from the message buffer to ensure data coherency. In this
situation, the read of the control/status word does not lock the message buffer.
Receive Message Buffer Deactivation
Locking and Releasing Message Buffers
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor