MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 44

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

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Figure
Number
Single Beat Basic Write Cycle Timing – One Wait State ...................................................... 9-14
Single Beat 32-Bit Data Write Cycle Timing — 16-Bit Port Size ......................................... 9-15
Read Followed by Write when Pre-Discharge Mode is Enabled, and EHTR is Set .............. 9-17
Basic Flow Diagram Of A Burst-Read Cycle......................................................................... 9-21
Burst-Read Cycle – 32-Bit Port Size – Zero Wait State......................................................... 9-21
Burst-Read Cycle – 32-Bit Port Size – One Wait State.......................................................... 9-22
Burst-Read Cycle – 32-Bit Port Size – Wait States Between Beats ....................................... 9-23
Burst-Read Cycle – 16-Bit Port Size ...................................................................................... 9-24
Basic Flow Diagram of a Burst-Write Cycle.......................................................................... 9-26
Burst-Write Cycle, 32-Bit Port Size, Zero Wait States
(Only for External Master Memory Controller Service Support)........................................... 9-26
Burst-Inhibit Read Cycle, 32-Bit Port Size (Emulated Burst)................................................ 9-27
Non-Wrap Burst with Three Beats ......................................................................................... 9-28
Non-Wrap Burst with One Data Beat ..................................................................................... 9-29
Internal Operand Representation ............................................................................................ 9-30
Interface To Different Port Size Devices................................................................................ 9-31
Bus Arbitration Flowchart ...................................................................................................... 9-33
Master Signals Basic Connection ........................................................................................... 9-34
Bus Arbitration Timing Diagram............................................................................................ 9-35
Internal Bus Arbitration State Machine .................................................................................. 9-36
Termination Signals Protocol Basic Connection .................................................................... 9-41
Termination Signals Protocol Timing Diagram...................................................................... 9-41
Reservation on Local Bus ....................................................................................................... 9-43
Reservation on Multi-level Bus Hierarchy ............................................................................. 9-44
Retry Transfer Timing – Internal Arbiter ............................................................................... 9-46
Retry Transfer Timing – External Arbiter .............................................................................. 9-47
Retry on Burst Cycle............................................................................................................... 9-48
Basic Flow of an External Master Read Access ..................................................................... 9-50
Basic Flow of an External Master Write Access .................................................................... 9-51
Peripheral Mode: External Master Reads from MPC561/MPC563 (Two Wait States) ......... 9-52
Peripheral Mode: External Master Writes to MPC561/MPC563 (Two Wait States)............ 9-53
Flow of Retry of External Master Read Access ..................................................................... 9-54
Retry of External Master Access (Internal Arbiter)................................................................ 9-55
Instruction Show Cycle Transaction....................................................................................... 9-57
Data Show Cycle Transaction................................................................................................. 9-58
Memory Controller Function within the USIU....................................................................... 10-1
Memory Controller Block Diagram........................................................................................ 10-2
MPC561/MPC563 Simple System Configuration .................................................................. 10-3
Bank Base Address and Match Structure ............................................................................... 10-4
A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts) ............................................. 10-9
MPC561/MPC563 Reference Manual, Rev. 1.2
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