MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 435
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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10.9.6
Freescale Semiconductor
,
1
10:12
13:27
28:30
Bits
HRESET
HRESET
It is recommended that this field hold values that are the power of 2 minus 1 (e.g., 2
7:9
31
Field
Field
Addr
Dual-Mapping Option Register (DMOR)
DMCS
MSB
Name
DME
—
16
0
AT
—
—
17
1
Reserved
Address type. This field can be used to specify that accesses involving the memory bank are
limited to a certain address space type. These bits are used in conjunction with the ATM bits
in the OR. The default value at reset is to map data only. For a full definition of address types,
refer to
Reserved
Dual-mapping chip select. This field determines which chip-select signal is assigned for dual
mapping.
000 CS0
001 CS1
010 CS2
011 CS3
1xx Reserved
Dual mapping enabled. This bit indicates that the contents of the dual-mapping registers and
associated base and option registers are valid and enables the dual-mapping operation. The
default value at reset comes from the internal data bus that reflects the reset configuration
word. See
information.
0 Dual mapping is not active
1 Dual mapping is active
18
2
Figure 10-26. Dual-Mapping Option Register (DMOR)
Section 9.5.8.6, “Address
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 10.5, “Dual Mapping of the Internal Flash EEPROM
AM
0000_0000_00
Table 10-11. DMBR Bit Descriptions
1
20
4
21
5
0000_0000_0000_0000
22
6
Types.”
0x2F C144
23
7
—
Description
—
24
8
25
9
10
26
ATM
001
3
11
27
- 1 = 7 [0b111]).
12
28
Array,” for more
13
29
Memory Controller
000
—
14
30
LSB
15
31
10-37
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