MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 474

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
During freeze mode, both the analog clock, QCLK, and periodic/interval timer are held in reset. When the
QADC64E enters the freeze mode while a queue is active, the current CCW location of the queue pointer
is saved.
During freeze, the analog clock, QCLK, is held in reset and the periodic/interval timer is held in reset.
External trigger events that occur during the freeze mode are not captured. The BIU remains active to
allow IMB3 access to all QADC64E registers and RAM. Although the QADC64E saves a pointer to the
next CCW in the current queue, the software can force the QADC64E to execute a different CCW by
writing new queue operating modes for normal operation. The QADC64E looks at the queue operating
modes, the current queue pointer, and any pending trigger events to decide which CCW to execute when
exiting freeze.
If the FRZ bit is clear, the internal FREEZE signal is ignored.
13.3.1.3
The LOCK and FLIP bits of the QADCMCR register control the operating mode of the QADC64E
modules. Out of reset, the QADC64E modules are in legacy mode (FLIP = 0) and the LOCK bit is clear,
indicating that the module is locked in legacy mode. In order to change the value of the FLIP bit, the
operating mode must first be unlocked, by setting the LOCK bit. Only then can the FLIP bit be changed.
Finally, the LOCK bit must be cleared again to protect the state of the FLIP bit from future writes.
13.3.1.4
The QADC64E memory map is divided into two segments: supervisor-only data space and assignable data
space. Access to supervisor-only data space is permitted only when the software is operating in supervisor
13-10
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1. Write LOCK = 1 to unlock operating mode bit.
2. Modify the value of FLIP as required.
3. Write LOCK = 0 and new FLIP bit value to preserve the value of FLIP bit
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If, during the execution of the current conversion, the queue operating mode for the active queue
is changed, or a queue 2 abort occurs, the QADC64E freezes immediately
— FLIP = 0 Legacy mode enabled
— FLIP = 1 Enhanced mode enabled
Example 1 Switching from legacy mode to enhanced mode
— QADCMCR = 0x280; LOCK =1, SUPV = 1
— QADCMCR = 0x380; LOCK =1, write FLIP = 1, SUPV = 1
— QADCMCR = 0x180; LOCK = 0, FLIP = 1, SUPV = 1
Subsequent writes to the FLIP bit will have no effect while LOCK = 0.
Example 2 Switching from enhanced mode to legacy mode
— QADCMCR = 0x280 or 0x380; LOCK = 1, SUPV =1
— QADCMCR = 0x280; LOCK = 1, FLIP = 0, SUPV = 1
— QADCMCR = 0x080; LOCK = 0, FLIP = 0, SUPV =1
(Can write FLIP = x because value will not change)
Switching Between Legacy and Enhanced Modes of Operation
Supervisor/Unrestricted Address Space
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor