MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 898

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CALRAM Operation
22.2
22.3
The MPC561/MPC563 chip internal memory map is shown in
The CALRAM module is divided into two sections.
TheMPC561/MPC563 contains one CALRAM module — a 32-Kbyte memory at address 0x3F 8000 –
0x3F FFFF as shown in
address spaces: 12 implemented and four unimplemented registers. The 12 implemented registers are: one
module configuration register (CRAMMCR), one register reserved for factory test, eight region base
address (CRAM_RBAx) registers, one overlay configuration register (CRAMOVLCR), and one
ownership trace register (CALRAM_OTR) to support a separate module called READI. Refer to
Chapter 24, “READI
22-2
•
•
Control section:
— Includes all the registers in the CALRAM module
Array sub-region:
— Contains memory arrays
CALRAM Block Diagram
CALRAM Memory Map
RPCU
FP
+
JTAG
Module.”
Figure 22-1
32-Kbytes CALRAM
4-Kbyte Overlay
28-Kbyte SRAM
(Non Overlay)
BBC
L-Bus
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 22-1. System Block Diagram
and
Figure
22-2. In addition, the module is assigned 16 32-bit register
READI
Flash
Interface
L2U
U-BUS
Figure
Interface
UIMB
22-2.
USIU
Freescale Semiconductor
E-Bus