MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 838

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Time Processor Unit 3
Table 19-5
prescaler).
19.4
The TPU3 memory map contains three groups of registers:
All registers except the channel interrupt status register (CISR) must be read or written by means of
half-word (16-bit) or word (32-bit) accesses. The address space of the TPU3 memory map occupies 512
bytes. Unused registers within the 512-byte address space return zeros when read.
Table 19-6
19-8
•
•
•
System configuration registers
Channel control and status registers
Development support and test verification registers
TCR2 Value
TCR2PSCK2
CLOCK
DIV8
TCR2
Pin
Programming Model
is a summary of prescaler output (assuming a divide-by-one value for the pre-divider
shows the TPU3 address map.
0b00
0b01
0b10
0b11
0x30 4000(TPU_A)
0x30 4400(TPU_B)
0x30 4002(TPU_A)
0x30 4402(TPU_B)
0x30 4004(TPU_A)
0x30 4404(TPU_B)
0x30 4006(TPU_A)
0x30 4406(TPU_B)
Address
Control
TCR2PSCK2 = 0
Mux
Internal Clock Divide Ratio
16
32
64
8
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 19-4. TCR2 Prescaler Control
Table 19-5. TCR2 Prescaler Control
Clock
Source
Table 19-6. TPU3 Register Map
TPU3 Module Configuration Register (TPUMCR)
See
TPU3 Test Configuration Register (TCR)
Development Support Control Register (DSCR)
See
Development Support Status Register (DSSR)
See
Table 19-7
Table 19-8
Table 19-9
TCR2PSCK2 = 1
Pre-divider
Prescaler
120
24
56
8
for bit descriptions.
for bit descriptions.
for bit descriptions.
Register
TCR2PSCK2 = 0
Prescaler
TCR2
External Clock Divide Ratio
1
2
4
8
Freescale Semiconductor
TCR2PSCK2 = 1
TCR2
15
1
3
7