MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 226

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Burst Buffer Controller 2 Module
4-20
24:25
Bits
19
20
21
22
23
26
DECOMP_SC_EN
EXC_COMP
EN_COMP
OERC[0:1]
BTEE
Name
ETRE
EIR
1
2
2
Table 4-4. BBCMCR Field Descriptions (continued)
2
Exception Table Relocation Enable
0 Exception Table Relocation is off: BBC does NOT map exception addresses.
1 Exception Table Relocation is on: BBC maps exception addresses to a table holding
The reset value is taken from the reset configuration word bit 19.
Note: On the MPC562/MPC564, do not put compressed code at addresses 0xFFF0
Enhanced External Interrupt Relocation Enable— This bit activates the external
interrupt relocation table mechanism. This bit is independent from the value of ETRE
bit, but if EIR and ETRE are enabled, the mapping of external interrupt will be via EIR.
0 EIR function is disabled.
1 EIR function is active.
Enable Compression. This bit enables the operation of the MPC562/MPC564 in
compression on mode.
NOTE: For Rev A and later versions of the MPC563 and rev B and later of the MPC561,
the default state is defined by bit 21 of the reset configuration word, and is writable. In
earlier versions, the bit can only be set by the reset configuration word.
0 decompression on mode is disabled.
1 decompression on mode is enabled.
The MPC561/MPC563 operates only in decompression off mode. The
MPC562/MPC564 may operate with both decompression on and decompression off
modes.
Exception Compression. This bit determines the operation of the MPC562/MPC564
with exceptions. If this bit is set, the MPC562/MPC564 assumes that the all exception
routine codes are compressed; otherwise it is assumed that all exception routine codes
are not compressed. The reset value is determined by reset configuration word bit 22.
0 The RCPU assumes that exception routines are noncompressed.
1 The RCPU assumes that all exception routines are compressed.
This bit has effects only when the EN_COMP bit is set. The MPC561/MPC563 operates
only in decompression off mode. The MPC562/MPC564 may operate with both
decompression on and decompression off modes.
Decompression Show Cycle Enable. This bit determines the way the MPC562/MPC564
executes instruction show cycles.
The reset value is determined by configuration word bit 21. For further details regarding
show cycles execution in “Decompression ON” mode see
“Decompression On
0 Decompression Show Cycles do not include the bit pointer.
1 Decompression Show Cycles include the bit pointer information on the data bus.
Other Exceptions Relocation Control. These bits have effect only if ETRE was enabled;
See details in
00: offset 0
01 Offset 64 Kbytes
10 Offset 512 Kbytes
11 Offset to 0x003FE000
The reset value is determined by reset configuration word bits 24 and 25
Branch Target Entries Enable. This bit enables Branch Target Entries of BTB operation
0 BTE operation is disabled
1 BTE operation is enabled
branch instructions two memory words apart from each other.
MPC561/MPC563 Reference Manual, Rev. 1.2
0000 to 0xFFFF FFFF if ETRE = 1.
Section 4.3.1, “ETR
Mode.”
Operation.”
Description
Section 4.2.1.2,
Freescale Semiconductor