MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 835

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

or with custom functions. Refer to Freescale Programming Note, Using the TPU Function Library and
TPU Emulation Mode (TPUPN00/D) for information about developing custom functions and accessing
the TPU function library. Refer to General TPU C Functions for the MPC500 Family (AN2360/D) for
more information about TPU functions in general and the TPU Literature Package (TPULITPAK/D) for
more information about specific functions.
19.3.7
Each of the TPU3 channels can generate an interrupt service request. Interrupts for each channel must be
enabled by writing to the appropriate control bit in the channel interrupt enable register (CIER). The
channel interrupt status register (CISR) contains one interrupt status flag per channel. Time functions set
the flags. Setting a flag bit causes the TPU3 to make an interrupt service request if the corresponding
channel interrupt enable bit is set.
The TPU3 can generate one of 32 possible interrupt request levels on the IMB3. The value driven onto
IRQ[7:0] represents the interrupt level programmed in the IRL field of the TPU interrupt configuration
register (TICR). Under the control of the ILBS bits in the ICR, each interrupt request level is driven during
one of four different time-multiplexed time slots, with eight levels communicated per time slot. No
hardware priority is assigned to interrupts. Furthermore, if more than one source on a module requests an
interrupt at the same level, the system software must assign a priority to each source requesting at that
level.
19.3.8
Timer count register 1 (TCR1) is clocked from the output of a prescaler. The following fields control
TCR1:
The rate at which TCR1 is incremented is determined as follows:
Freescale Semiconductor
•
•
•
•
Figure 19-2
The PSCK and TCR1P fields in TPUMCR
The DIV2 field in TPUMCR2
The EPSCKE and EPSCK fields in TPUMCR3.
The user selects either the standard prescaler (by clearing the enhanced prescaler enable bit,
EPSCKE, in TPUMCR3) or the enhanced prescaler (by setting EPSCKE).
— If the standard prescaler is selected (EPSCKE = 0), then the PSCK bit determines whether the
ILBS[1:0]
IMB3 CLOCK
IMB3 IRQ[7:0]
standard prescaler divides the system clock input by 32 (PSCK = 0) or 4 (PSCK = 1)
TPU3 Interrupts
Prescaler Control for TCR1
displays the interrupt level scheme.
00
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 19-2. TPU3 Interrupt Levels
01
IRQ
7:0
10
IRQ
15:8
23:16
11
IRQ
31:24
00
IRQ
01
IRQ
7:0
10
11
Time Processor Unit 3
19-5