MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 964
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 964 of 1420
- Download datasheet (11Mb)
Development Support
Note: LCTRL2 is cleared following reset.
For each watchpoint, three control register fields (LWxIA, LWxLA, LWxLD) must be programmed. For
a watchpoint to be asserted, all three conditions must be detected.
23-50
14:15
17:18
21:27
Bits
16
19
20
28
29
30
31
BRKNOMSK
LW1LADC
LW1LDDC
DLW0EN
DLW1EN
SLW0EN
SLW1EN
LW1LA
LW1LD
Name
—
Table 23-25. LCTRL2 Bit Descriptions (continued)
2nd L-bus watchpoint
L-addr events selection
00 match from comparator E
01 match from comparator F
10 match from comparators (E&F)
11 match from comparators (E | F)
2nd L-bus watchpoint
care/don’t care L-addr events
0 Don’t care
1 Care
2nd L-bus watchpoint
L-data events selection
00 match from comparator G
01 match from comparator H
10 match from comparators (G&H)
11 match from comparator (G | H)
2nd L-bus watchpoint
care/don’t care L-data events
0 Don’t care
1 Care
Internal breakpoints non-mask bit
0 masked mode; breakpoints are recognized only when MSR[RI]=1 (reset value)
1 non-masked mode; breakpoints are always recognized
Reserved
Development port trap enable selection of the 1st L-bus watchpoint
(read only bit)
0 trap disabled (reset value)
1 trap enabled
Development port trap enable selection of the 2nd L-bus watchpoint
(read only bit)
0 trap disabled (reset value)
1 trap enabled
Software trap enable selection of the 1st L-bus watchpoint
0 trap disabled (reset value)
1 trap enabled
Software trap enable selection of the 2nd L-bus watchpoint
0 trap disabled (reset value)
1 trap enabled
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Freescale Semiconductor
Related parts for MPC561MZP56
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
MPC5 1K0 5%
Manufacturer:
TE Connectivity
Datasheet:
Part Number:
Description:
MPC5 500R 5%
Manufacturer:
TE Connectivity
Datasheet:
Part Number:
Description:
MPC5 5K0 5%
Manufacturer:
Tyco Electronics
Datasheet:
Part Number:
Description:
MPC5 5R0 5%
Manufacturer:
Tyco Electronics
Datasheet:
Part Number:
Description:
MPC5 50K 5%
Manufacturer:
Tyco Electronics
Datasheet:
Part Number:
Description:
MPC5 1R0 5%
Manufacturer:
Tyco Electronics
Datasheet:
Part Number:
Description:
TOWER ELEVATOR BOARDS HARDWARE
Manufacturer:
Freescale Semiconductor
Datasheet:
Part Number:
Description:
TOWER SERIAL I/O HARDWARE
Manufacturer:
Freescale Semiconductor
Datasheet:
Part Number:
Description:
LCD MODULE FOR TWR SYSTEM
Manufacturer:
Freescale Semiconductor
Datasheet:
Part Number:
Description:
DAUGHTER LCD WVGA I.MX51
Manufacturer:
Freescale Semiconductor
Datasheet:
Part Number:
Description:
TOWER SYSTEM BOARD MPC5125
Manufacturer:
Freescale Semiconductor
Datasheet: