MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 281

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

register may be written by the mttbl or the mttbu instructions, see
—
Refer to
—
6.2.2.4.3
Two reference registers (TBREF0 and TBREF1) are associated with the lower part of the time base (TBL).
Each is a 32-bit read/write register. Upon a match between the contents of TBL and the reference register,
a maskable interrupt is generated.
Freescale Semiconductor
OEA.”
OEA” for more information on reading and writing the TBU and TBL registers.
PORESET
Reset
Reset
PORESET
Field
Field
Addr
Addr
Field
Section 3.8, “VEA Register Set — Time Base
Addr
Field
Addr
MSB
MSB
0
0
MSB
Time Base Reference Registers (TBREF0 and TBREF1)
MSB
0
0
Figure 6-32. Time Base Reference Register 0 (TBREF0)
Figure 6-33. Time Base Reference Register 1 (TBREF1)
MPC561/MPC563 Reference Manual, Rev. 1.2
TBU
Figure 6-30. Time Base (Reading) (TB)
TBU
Figure 6-31. Time Base (Writing) (TB)
SPR 269, SPR 268
SPR 285, SPR 284
Unaffected
0x2F C204
0x2F C208
Unaffected
TBREF0
TBREF1
Unaffected
Unaffected
(TB)’ and
31 32
31 32
Section 3.9.4, “Time Base Facility (TB)
Section 3.9.4, “Time Base Facility (TB)
System Configuration and Protection
TBL
TBL
LSB
LSB
63
31
LSB
LSB
31
63
6-41