MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 729

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

16.7.13 Interrupt Mask Register (IMASK)
Freescale Semiconductor
SRESET
Bits
13
14
15
Field
Addr
MSB
0
WAKEINT
BOFFINT
ERRINT
Name
1
BITERR[1:0]
00
01
10
11
2
Bus off interrupt. The BOFFINT bit is used to request an interrupt when the TouCAN enters
the bus off state.
0 No bus off interrupt requested
1 When the TouCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in
Error Interrupt. The ERRINT bit is used to request an interrupt when the TouCAN detects a
transmit or receive error.
0 No error interrupt request
1 If an event which causes one of the error bits in the error and status register to be set
To clear this bit, first read it as a one, then write as a zero. Writing a one has no effect.
Wake interrupt. The WAKEINT bit indicates that bus activity has been detected while the
TouCAN module is in low-power stop mode.
0 No wake interrupt requested
1 When the TouCAN is in low-power stop mode and a recessive to dominant transition is
CANCTRL0 is set, an interrupt request is generated. This interrupt is not requested after
reset.
occurs, the error interrupt bit is set. If the ERRMSK bit in CANCTRL0 is set, an interrupt
request is generated.
detected on the CAN bus, this bit is set. If the WAKEMSK bit is set in CANMCR, an
interrupt request is generated.
0x30 70A2 (IMASK_A); 0x30 74A2 (IMASK_B); 0x30 78A2 (IMASK_C)
Table 16-23. ESTAT Bit Descriptions (continued)
Table 16-25. Fault Confinement State Encoding
Figure 16-20. Interrupt Mask Register (IMASK)
IMASKH
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 16-24. Transmit Bit Error Status
No transmit bit error
At least one bit sent as dominant was received as recessive
At least one bit sent as recessive was received as dominant
Not used
FCS[1:0]
4
1X
00
01
5
0000_0000_0000_0000
6
7
Bit Error Status
Error passive
Error active
Bus State
Description
Bus off
8
9
10
IMASKL
11
12
CAN 2.0B Controller Module
13
14
LSB
15
16-35