MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 956

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Development Support
23-42
SRESET
SRESET
11:12
Field — RST CHSTP
Field — SEE
Addr
Bits
4:5
10
13
14
15
16
17
18
19
20
21
0
1
2
3
6
7
8
9
MSB
16
0
DTLBER
ITLBER
CHSTP
FPUVE
FPASE
Name
DECE
SYSE
MCE
EXTI
PRE
RST
SEE
ALE
TR
17
—
—
—
—
—
—
1
—
18
2
Reserved
Reset interrupt bit. This bit is set when the system reset pin is asserted.
Checkstop bit. Set when the processor enters checkstop state.
Machine check interrupt bit. Set when a machine check exception (other than one caused by a
data storage or instruction storage error) is asserted.
Reserved
External interrupt bit. Set when the external interrupt is asserted.
Alignment exception bit. Set when the alignment exception is asserted.
Program exception bit. Set when the program exception is asserted.
Floating point unavailable exception bit. Set when the program exception is asserted.
Decrementer exception bit. Set when the decrementer exception is asserted.
Reserved
System call exception bit. Set when the system call exception is asserted.
Trace exception bit. Set when in single-step mode or when in branch trace mode.
Floating point assist exception bit. Set when the floating point assist exception occurs.
Reserved
Software emulation exception. Set when the software emulation exception is asserted.
Reserved
Implementation specific instruction protection error
This bit is set as a result of an instruction protection error. Results in debug mode entry if debug
mode is enabled and the corresponding enable bit is set.
Reserved
Implementation specific data protection error
This bit is set as a result of an data protection error. Results in debug mode entry if debug mode
is enabled and the corresponding enable bit is set.
ITLBER —
MCE
19
3
Figure 23-16. Exception Cause Register (ECR)
MPC561/MPC563 Reference Manual, Rev. 1.2
20
4
Table 23-18. ECR Bit Descriptions
DTLBER
—
21
5
0000_0000_0000_0000
0000_0000_0000_0000
EXTI ALE PRE FPUVE DECE
22
6
SPR 148
23
7
Description
24
8
—
25
9
10
26
11
27
LBRK IBRK EBRK
—
12
28
SYSE
Freescale Semiconductor
13
29
TR
14
30
FPASE
LSB
DPI
15
31