MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 179

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Note that exceptions can occur while an exception handler routine is executing, and multiple exceptions
can become nested. It is up to the exception handler to save the appropriate machine state if it is desired
that control be returned to the excepting program.
In many cases, after the exception handler handles an exception, there is an attempt to execute the
instruction that caused the exception. Instruction execution continues until the next exception condition is
encountered. This method of recognizing and handling exception conditions sequentially guarantees that
the machine state is recoverable and processing can resume without losing instruction results.
To prevent the loss of state information, exception handlers must save the information stored in SRR0 and
SRR1 soon after the exception is taken to prevent this information from being lost due to another exception
being taken.
3.11.1
The RCPU exception classes are shown in
3.11.2
In the RCPU, all exceptions except for reset, debug port non-maskable interrupts, and machine check
exceptions are ordered. Ordered exceptions satisfy the following criteria:
3.11.3
Unordered exceptions may be reported at any time and are not guaranteed to preserve program state
information. The processor can never recover from a reset exception. It can recover from other unordered
exceptions in most cases. However, if a debug port non-maskable interrupt or machine check exception
occurs during the servicing of a previous exception, the machine state information in SRR0 and SRR1
(and, in some cases, the DAR and DSISR) may not be recoverable; the processor may be in the process of
saving or restoring these registers.
To determine whether the machine state is recoverable, the RI (recoverable exception) bit in SRR1 can be
read. During exception processing, the RI bit in the MSR is copied to SRR1 and then cleared. The
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Only one exception is reported at a time. If, for example, a single instruction encounters multiple
exception conditions, those conditions are encountered sequentially. After the exception handler
handles an exception, instruction execution continues until the next exception condition is
encountered.
When the exception is taken, no program state is lost.
Exception Classes
Ordered Exceptions
Unordered Exceptions
Synchronous (ordered, precise)
Asynchronous, unordered
Asynchronous, ordered
MPC561/MPC563 Reference Manual, Rev. 1.2
Class
Table 3-18. RCPU Exception Classes
Table
3-18.
Instruction-caused exceptions
External interrupt
Exception Type
Machine check
System reset
Decrementer
Central Processing Unit
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