MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 91

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

1.3.3.3
1.3.3.4
Freescale Semiconductor
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12 dedicated PWM sub-modules (PWMSM)
One MIOS14 16-bit parallel port I/O sub-modules (MPIOSM)
Two queued analog-to-digital converter modules (QADC64E_A, QADC64E_B) providing a total
of 32 analog channels
16 analog input channels on each QADC64E module using internal multiplexing
Directly supports up to four external multiplexers
Up to 41 total input channels on the two QADC64E modules with external multiplexing
Software configurable to operate in enhanced or legacy (MPC555 compatible) mode
Unused analog channels can be used as digital input/output signals
— GPIO on all channels in enhanced mode
10-bit A/D converter with internal sample/hold
Minimum conversion time of 7 µs (with typical QCLK frequency, 2 MHz) and +/- 2 bits accuracy
Two conversion command queues of variable length
Automated queue modes initiated by:
— External edge trigger
— Software command
— Periodic/interval timer within the QADC64E module, that can be assigned to both queue 1 and
— External gated trigger (queue 1 only)
64 result registers
— Output data is right- or left-justified, signed or unsigned.
Alternate reference input (ALTREF), with control in the conversion command word (CCW)
Three TouCAN modules (TouCAN_A, TouCAN_B, TouCAN_C)
Each TouCAN provides the following features:
— 16 message buffers, programmable I/O modes
— Maskable interrupts
— Independent of the transmission medium (external transceiver is assumed)
— Open network architecture, multi-master concept
— High immunity to EMI
— Short latency time for high-priority messages
— Low-power sleep mode, with programmable wake-up on bus activity
— TouCAN_C pins are shared with MIOS14 GPIO or QSMCM
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Two Enhanced Queued Analog-to-Digital Converter Modules
(QADC64E)
Three CAN 2.0B Controller (TouCAN) Modules
MPC561/MPC563 Reference Manual, Rev. 1.2
Overview
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