MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 287

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

6.2.2.5.2
Freescale Semiconductor
1
If the device is configured NOT in full bus mode (i.e., SIUMCR[SC]=0b01, 0x10, or 0b11), the GPIO pins will be in input
Reset
Reset
mode and this register will reflect the state of the pins.
16:23
24:31
Field
Field
Addr
Bits
8:15
0:7
MSB
16
0
SGPIOA[8:15] SIU general-purpose I/O Group A[8:15]. This 8-bit register controls the data of the
SGPIOC[0:7] SIU general-purpose I/O Group C[0:7]. This 8-bit register controls the data of the
SGPIO Data Register 2 (SGPIODT2)
SGPIOA
SGPIOA
[16:23]
[24:31]
Name
17
1
18
2
general-purpose I/O pins SGPIOC[0:7]. The direction of SGPIOC[0:7] is controlled by 8
dedicated direction control signals SDDRC[0:7] in the SGPIO control register. Each pin in
this group can be configured separately as general-purpose input or output.
general-purpose I/O pins SGPIOA[8:15]. The GDDR3 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
SIU general-purpose I/O Group A[16:23]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOA[16:23]. The GDDR4 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
SIU general-purpose I/O Group A[24:31]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOA[24:31]. The GDDR5 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
SGPIOA[16:23]
SGPIOC[0:7]
19
3
Figure 6-42. SGPIO Data Register 2 (SGPIODT2)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 6-24. SGPIODT2 Bit Descriptions
20
4
21
5
0000_0000_0000_0000
0000_0000_0000_0000
22
6
0x2F C028
23
7
24
Description
8
25
9
1
1
10
26
SGPIOA[24:31]
SGPIOA[8:15]
11
27
System Configuration and Protection
12
28
13
29
14
30
LSB
15
31
6-47