MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 413

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Figure 10-12
note the following points:
Freescale Semiconductor
•
•
•
•
Total cycle length = 5, is determined as follows:
— Two clocks for basic cycle
— SCY = 1 determines 1 wait state, which is multiplied by two due to TRLX being set (2 + (SCY
— Extra clock is added due to TRLX effect on the strobes.
Because TRLX is set, assertion of the CS and WE strobes is delayed by one clock cycle.
CS assertion is delayed an additional one quarter clock cycle because ACS = 10.
The total cycle length = three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— An extra clock cycle is required due to the effect of TRLX on the strobes.
Address
x 2)).
CLOCK
RD/WR
WE/BE
through
Data
Figure 10-11. Relaxed Timing — Read Access (ACS = 11, SCY = 1, TRLX = 1)
OE
CS
TS
TA
Figure 10-14
MPC561/MPC563 Reference Manual, Rev. 1.2
are examples of write accesses using relaxed timing. In
ACS = ‘00’ & TRLX = ‘1’
ACS = ‘11’ & TRLX = ‘1’
WEBS = ‘1’,Line Acts as BE
in Read.
Memory Controller
Figure
10-12,
10-15