MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 811

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

18.3.1.2
The PPM module generates and outputs two clock signals, PPM_TCLK and PPM_TSYNC. The
PPM_TCLK and PPM_TSYNC clocks are the basis for all PPM communication functions; single data bits
are transmitted and received on PPM_TCLK cycles, one PPM_TSYNC clock cycle defines a single 16-bit
word transmit/receive cycle. The PPM can be configured to transfer data in one of two clock modes, SPI
and TDM.
PPM_TCLK is a function of the system clock (SYSCLK) and is programmable using the
Freescale Semiconductor
A_TPUCH15
B_TPUCH15
A_TPUCH0
B_TPUCH0
A_TPUCH15
B_TPUCH15
A_TPUCH0
B_TPUCH0
Figure 18-5
MPWM0
GPDO15
MDA14
MPWM0
PPM Clocks
GPDO0
MDA14
Figure 18-4. Internal Multiplexer Mechanism for Received Data
Figure 18-3. Internal Multiplexer Mechanism for Transmit Data
shows examples of PPM_TCLK in SPI and TDM modes. The frequency of
MPC561/MPC563 Reference Manual, Rev. 1.2
RX_CONFIG[CH0]
RX_CONFIG[CH15]
TX_CONFIG[CH15]
TX_CONFIG[CH0]
CH15
CH15
CH15
CH15
RX_DATA
GPDI
RX_SHIFTER
TX_SHIFTER
• • •
• • •
• • •
• • •
Peripheral Pin Multiplexing (PPM) Module
RX_CONFIG[CHx]
CH0
CH0
CH0
CH0
PPM_RX[0:1]
PPM_TX[0:1]
•
18-5