MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 901

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

22.4.1
Reset configures the CALRAM module and resets some of the bits in the CALRAM registers to their
default reset state. Some register bits are unaffected by reset. See section
Model.”
22.4.2
The CALRAM registers and array may be accessed for reads or writes as byte, (aligned) half-word, or
word. This mode is the default mode of operation and, as the name suggests, the access time to the array
and the internal registers for reads and writes is one cycle. Thus the one-cycle mode is used for high
performance although it consumes more power than the two cycle mode.
22.4.2.1
Each 8-Kbyte CALRAM array can be assigned read-only, data-only, or supervisor-only privilege if data
relocate (DR) bit in the MSR is set. All CALRAM registers are assigned supervisor-only and data-only
privilege. A privilege violation causes an error. See section
Configuration Register
An attempt to access any of the four unimplemented reserved registers (of the 16 register spaces) causes
an error and returns 0’s on the data bus for a read access. If an error condition occurs due to privilege
violation or an attempt to access unimplemented portions of array or register space, then the type of the
error generated depends on whether the access generating the error was initiated by the RCPU core or by
a non-RCPU bus master. If the error causing access was initiated by the RCPU core, a data storage
interrupt (DSI) is generated. If the access was initiated by a non-RCPU bus master, a machine check
exception is generated. Also, a write access that generates an error does not corrupt the data in an array or
a register. Similarly, a read access that generates an error does not drive the data on the L-bus from the
array or the register, instead it drives 0’s. Also, aborted accesses maintain data integrity. Aborted writes do
not corrupt data in register/array, and aborted reads do not drive the requested data on L-bus.
22.4.3
In this mode, the CALRAM module takes two cycles to complete an access and consumes less power than
in one-cycle mode. It follows the normal one-cycle mode operation except that the accesses are completed
one cycle later. This mode is selected by setting the 2CY bit in the CRAMMCR register.
22.4.4
The registers and control logic for the CALRAM module are powered by VDD
supplied by VDD during normal operation; however, when the VDD is off, the CALRAM array is backed
up by a switched source (IRAMSTBY) that is also known as standby power.
Freescale Semiconductor
Reset
One-Cycle Mode
Two-Cycle Mode
Standby Operation/Keep-Alive Power
CALRAM Access/Privilege Violations
(CRAMMCR).”
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 22.5.1, “CALRAM Module
Section 22.5, “Programming
.
The memory array is also
CALRAM Operation
22-5