MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 461
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
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Quantity:
10 000
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Part Number:
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Any word, half-word or byte access to a 32-bit location within the UIMB interface register decode block
that is unimplemented (defined as reserved) causes the UIMB interface to assert a data error exception on
the U-bus.The entire 32-bit location must be defined as reserved in order for a data error exception to be
asserted.
Unimplemented bits in a register return zero when read.
12.5.1
The UIMB module configuration register (UMCR) is accessible in supervisor mode only.
Freescale Semiconductor
HRESET
HRESET
1
Access
Field STOP
Field
Addr
S = Supervisor mode only; T = Test mode only
S/T
—
S
UIMB Module Configuration Register (UMCR)
MSB
1
16
0
0
0x30 7F94 — 0x30 7F9F Reserved
IRQMUX
17
1
Base Address
00
0x30 7F90
0x30 7FA0
Figure 12-7. UIMB Module Configuration Register (UMCR)
18
2
Table 12-5. UIMB Interface Register Map (continued)
HSPEED
19
1
3
MPC561/MPC563 Reference Manual, Rev. 1.2
UIMB Test Control Register (UTSTCREG)
Reserved
Pending Interrupt Request Register (UIPEND)
See
descriptions.
20
4
Section 12.5.3, “Pending Interrupt Request Register
21
5
0000_0000_0000_0000
22
6
0x30 7F80
23
7
—
24
8
0000_0000_0000
Register
25
9
—
10
26
U-Bus to IMB3 Bus Interface (UIMB)
11
27
12
28
(UIPEND)” for bit
13
29
14
30
LSB
15
31
12-7
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