MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 53

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

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21-10
21-11
22-1
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23-25
Freescale Semiconductor
Figure
Number
Program State Diagram......................................................................................................... 21-23
Erase State Diagram.............................................................................................................. 21-27
Censorship States and Transitions ........................................................................................ 21-33
System Block Diagram ........................................................................................................... 22-2
MPC561/MPC563 Memory Map with CALRAM Address Ranges ...................................... 22-3
Standby Power Supply Configuration for CALRAM Array .................................................. 22-4
CALRAM Array ..................................................................................................................... 22-7
CALRAM Module Overlay Map of Flash (CLPS = 0) .......................................................... 22-8
CALRAM Address Map (CLPS = 0) ..................................................................................... 22-9
CALRAM Module Overlay Map of Flash (CLPS = 1) ........................................................ 22-10
CALRAM Address Map (CLPS = 1) ................................................................................... 22-11
CALRAM Module Configuration Register (CRAMMCR).................................................. 22-13
CALRAM Region Base Address Register (CRAM_RBAx) ................................................ 22-16
CALRAM Overlay Configuration Register (CRAM_OVLCR)........................................... 22-17
CALRAM Ownership Trace Register (CRAM_OTR) ......................................................... 22-18
Watchpoint and Breakpoint Support in the CPU.................................................................... 23-9
Partially Supported Watchpoint/Breakpoint Example.......................................................... 23-13
Instruction Support General Structure .................................................................................. 23-15
Load/Store Support General Structure.................................................................................. 23-18
Functional Diagram of MPC561/MPC563 Debug Mode Support ....................................... 23-21
Debug Mode Logic ............................................................................................................... 23-23
BDM Mode Selection ........................................................................................................... 23-24
Debug Mode Reset Configuration ........................................................................................ 23-25
Asynchronous Clock Serial Communications ...................................................................... 23-32
Synchronous Self Clock Serial Communication .................................................................. 23-32
Enabling Clock Mode Following Reset................................................................................ 23-33
Download Procedure Code Example .................................................................................... 23-37
Slow Download Procedure Loop .......................................................................................... 23-38
Fast Download Procedure Loop ........................................................................................... 23-38
Comparator A–D Value Register (CMPA–CMPD).............................................................. 23-41
Exception Cause Register (ECR).......................................................................................... 23-42
Debug Enable Register (DER).............................................................................................. 23-43
Breakpoint Counter B Value and Control Register (COUNTB) .......................................... 23-46
Comparator E–F Value Registers (CMPE–CMPF) .............................................................. 23-46
Comparator G–H Value Registers (CMPG–CMPH)............................................................ 23-47
L-Bus Support Control Register 1 (LCTRL) ........................................................................ 23-47
L-Bus Support Control Register 2 (LCTRL2) ...................................................................... 23-48
I-Bus Support Control Register (ICTRL) ............................................................................. 23-51
Breakpoint Address Register (BAR) .................................................................................... 23-53
Breakpoint Counter A Value and Control Register (COUNTA)......................................... 23-45
MPC561/MPC563 Reference Manual, Rev. 1.2
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