MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 562

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Enhanced Mode Operation
Table 14-14
14-20
Bits
9:15
shows the bits in the MQ2 field which enable different queue 2 operating modes.
Name
BQ2
MQ2[3:7]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
Beginning of queue 2. The BQ2 field indicates the CCW location where queue 2 begins. To
allow the length of queue 1 and queue 2 to vary, a programmable pointer identifies the CCW
table location where queue 2 begins. The BQ2 field also serves as an end-of-queue condition
for queue 1. Setting BQ2 beyond physical CCW table memory space allows queue 1 all 64
entries.
Software defines the beginning of queue 2 by programming the BQ2 field in QACR2. BQ2 is
usually programmed before or at the same time as the queue operating mode for queue 2 is
selected. If BQ2 is 64 or greater, queue 2 has no entries, and the entire CCW table is
dedicated to queue 1 and CCW63 is the end-of-queue 1. If BQ2 is zero, the entire CCW table
is dedicated to queue 2. As a special case, when a queue operating mode for queue 1 is
selected and a trigger event occurs for queue 1 with BQ2 set to zero, queue 1 execution is
terminated after CCW0 is read. Conversions do not occur.
The BQ2 pointer may be changed dynamically, to alternate between queue 2 scan
sequences. A change in BQ2 after queue 2 has begun or if queue 2 has a trigger pending
does not affect queue 2 until queue 2 is started again.For example, two scan sequences
could be defined as follows: the first sequence starts at CCW10, with a pause after CCW11
and an EOQ programmed in CCW15; the second sequence starts at CCW16, with a pause
after CCW17 and an EOQ programmed in CCW39.
With BQ2 set to CCW10 and the continuous-scan mode selected, queue execution begins.
When the pause is encountered in CCW11, a software interrupt routine can redefine BQ2 to
be CCW16. Therefore, after the end-of-queue is recognized in CCW15, an internal retrigger
event is generated and execution restarts at CCW16. When the pause software interrupt
occurs again, software can change BQ2 back to CCW10. After the end-of-queue is
recognized in CCW39, an internal retrigger event is created and execution now restarts at
CCW10.
If BQ2 is changed while queue 1 is active, the effect of BQ2 as an end-of-queue indication
for queue 1 is immediate. However, beware of the risk of losing the end-of-queue 1 through
moving BQ2. Recommend use of EOQ (chan63) to end queue 1.
Note: Be sure to do a mode change when changing BQ2 and setting SSE2. Setting BQ2 first
Table 14-13. QACR2 Bit Descriptions (continued)
is recommended.
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE2)
External trigger rising edge single-scan mode
External trigger falling edge single-scan mode
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 14-14. Queue 2 Operating Modes
Operating Modes
Description
7
8
9
10
11
12
Freescale Semiconductor